ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 26

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.5.7 Output codes versus input voltage
11.6.1 Register description
11.6 Serial peripheral interface
Table 16.
The ADC1210S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on pin CS. A minimum of three bytes
is transmitted (two instruction bytes and at least one data byte). The number of data bytes
is determined by the value of bits W1 and W2 (see
Table 17.
[1]
[2]
V
< 1
1.0000000
0.9995117
0.9990234
0.9985352
0.9980469
....
0.0009766
0.0004883
0.0000000
+0.0004883
+0.0009766
....
+0.9980469
+0.9985352
+0.9990234
+0.9995117
+1.0000000
> +1
Bit
Description
INP
Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see
 V
INM
Output codes
Instruction bytes for the SPI
Offset binary
0000 0000 0000
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
....
0111 1111 1110
0111 1111 1111
1000 0000 0000
1000 0000 0001
1000 0000 0010
....
1111 1111 1011
1111 1111 1100
1111 1111 1101
1111 1111 1110
1111 1111 1111
1111 1111 1111
All information provided in this document is subject to legal disclaimers.
MSB
7
A7
R/W
Rev. 2 — 23 December 2010
[1]
6
W1
A6
[2]
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
5
W0
A5
[2]
4
A12
A4
Two’s complement
1000 0000 0000
1000 0000 0000
1000 0000 0001
1000 0000 0010
1000 0000 0011
1000 0000 0100
....
1111 1111 1110
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0010
....
0111 1111 1011
0111 1111 1100
0111 1111 1101
0111 1111 1110
0111 1111 1111
0111 1111 1111
Table
ADC1210S series
3
A11
A3
18).
2
A10
A2
© NXP B.V. 2010. All rights reserved.
1
A9
A1
OTR pin
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table
LSB
0
A8
A0
26 of 39
18).