ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 25

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.5.3 DAta Valid (DAV) output clock
11.5.4 Out-of-Range (OTR)
11.5.5 Digital offset
11.5.6 Test patterns
Table 14.
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1210S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR
(bit FASTOTR = logic 1; see
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
Table 15.
By default, the ADC1210S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see
For test purposes, the ADC1210S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see
can be defined by the user (TESTPAT_USER[11:0]; see
selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted
regardless of the analog input.
LVDS_INT_TER[2:0]
000
001
010
011
100
101
110
111
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
and
LVDS DDR output register 2
Fast OTR register
Figure 5
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 December 2010
respectively.
Table
Table
25).
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
29). In this mode, the latency of OTR is reduced to only
Resistor value ()
no internal termination
300
180
110
150
100
81
60
Detection level (dB)
20.56
16.12
11.02
7.82
5.49
3.66
2.14
0.86
ADC1210S series
Table 27
Table
26). A custom test pattern
and
Table
© NXP B.V. 2010. All rights reserved.
28) and is
25 of 39