ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 32

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
Table 24.
Default values are highlighted.
Table 25.
Default values are highlighted.
Table 26.
Default values are highlighted.
ADC1210S_SER
Product data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 6
5 to 0
Bit
7 to 3
2 to 0
Symbol
-
DAVINV
DAVPHASE[2:0]
Symbol
-
DIG_OFFSET[5:0]
Symbol
-
TESTPAT_SEL[2:0]
Output clock register (address 0012h) bit description
Offset register (address 0013h) bit description
Test pattern register 1 (address 0014h) bit description
Access
R/W
R/W
Access
R/W
Access
R/W
All information provided in this document is subject to legal disclaimers.
Value
0000
0
1
000
001
010
011
100
101
110
111
Rev. 2 — 23 December 2010
Value
00
011111
...
000000
...
100000
Value
00000
000
001
010
011
100
101
110
111
output clock data valid (DAV) polarity
Description
not used
DAV phase select
normal
inverted
output clock shifted (ahead) by 6/16  t
output clock shifted (ahead) by 5/16  t
output clock shifted (ahead) by 4/16  t
output clock shifted (ahead) by 3/16  t
output clock shifted (ahead) by 2/16  t
output clock shifted (ahead) by 1/16  t
default value as defined in timing section
output clock shifted (delayed) by 1/16  t
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Description
not used
digital test pattern select
Description
not used
digital offset adjustment
off
mid scale
FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
+31 LSB
...
0
...
32 LSB
ADC1210S series
clk
clk
clk
clk
clk
clk
clk
© NXP B.V. 2010. All rights reserved.
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