ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 21

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.3.3 Common-mode output voltage (V
11.3.4 Biasing
11.4.1 Drive modes
11.4 Clock input
A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
The common-mode input voltage (V
0.5V
The ADC1210S can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 25. Equivalent schematic of the common-mode reference circuit
Fig 26. LVCMOS single-ended clock input
DDA
a. Rising edge LVCMOS
for optimal performance and should always be between 0.9 V and 2 V.
0.1 μF
clock input
1.5 V
VCM
LVCMOS
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 December 2010
package
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CLKM
CLKP
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
ESD
I(cm)
O(cm)
) on pins INP and INM should be set externally to
parasitics
)
b. Falling edge LVCMOS
ADC1210S series
COMMON-MODE
REFERENCE
clock input
LVCMOS
ADC core
© NXP B.V. 2010. All rights reserved.
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CLKM
CLKP
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