ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 23

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.4.3 Duty cycle stabilizer
11.4.4 Clock input divider
11.5.1 Digital output buffers: CMOS mode
11.5 Digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table
bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
The ADC1210S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in
supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from
the ADC core. Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
Table
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DRIVER
23).
LOGIC
Rev. 2 — 23 December 2010
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Figure
Table
50 Ω
Table
29. The buffer is powered by a separate power
21), the circuit can handle signals with duty
Parasitics
21). This feature allows the user to deliver a
ESD
ADC1210S series
Package
005aaa057
© NXP B.V. 2010. All rights reserved.
VDDO
Dx
OGND
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