ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 28

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ADC1210S065HN/C1:5

Manufacturer Part Number
ADC1210S065HN/C1:5
Description
ADC1210S065HN/HVQFN40/REEL13DP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ADC1210S065HN/C1:5

Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Serial, SPI™
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935289036518
ADC1210S065HN,518
ADC1210S065HN,518
NXP Semiconductors
ADC1210S_SER
Product data sheet
Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
(CMOS LVDS DDR)
(CMOS LVDS DDR)
All information provided in this document is subject to legal disclaimers.
SDIO
SDIO
Rev. 2 — 23 December 2010
CS
CS
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Offset binary, LVDS DDR
default mode at start-up
two's complement, CMOS
default mode at start-up
ADC1210S series
© NXP B.V. 2010. All rights reserved.
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