ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 24

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.5.2 Digital output buffers: LVDS DDR mode
The output resistance is 50  and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see
Each output should be terminated externally with a 100  resistor (typical) at the receiver
side
Table
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
(Figure
32).
Table
30) or internally via SPI control bits LVDS_INT_TER[2:0] (see
All information provided in this document is subject to legal disclaimers.
−
+
−
+
23).
Rev. 2 — 23 December 2010
3.5 mA
typ
3.5 mA
typ
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
100 Ω
+
−
+
−
VDDO
D
D
OGND
VDDO
D
D
OGND
x
x
x
x
P/D
M/D
P/D
M/D
Table
x + 1
x + 1
x + 1
x + 1
P
P
M
M
31) in order to adjust the output logic
ADC1210S series
100 Ω
RECEIVER
RECEIVER
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005aaa059
© NXP B.V. 2010. All rights reserved.
Table
Figure 31
30).
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