ADSP-21062LABZ-160 Analog Devices Inc, ADSP-21062LABZ-160 Datasheet - Page 4

• Manufacturer Part Number: ADSP-21062LABZ-160
• Description: IC,DSP,32-BIT,CMOS,BGA,225PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21062LABZ-160

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-BGA
• Package: 225BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 40 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
GENERAL DESCRIPTION
The ADSP-2106x SHARC
puter—is a 32-bit signal processing microcomputer that offers
high levels of DSP performance. The ADSP-2106x builds on the
ADSP-21000 DSP core to form a complete system-on-a-chip,
adding a dual-ported on-chip SRAM and integrated I/O periph-
erals supported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle.
mance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including up to 4M bit SRAM memory (see
host processor interface, DMA controller, serial ports and link
port, and parallel bus connectivity for glueless DSP
multiprocessing.
Table 2. Benchmarks (at 40 MHz)
The ADSP-2106x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram
tural features:
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
• Computation units (ALU, multiplier and shifter) with a
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Interval timer
• On-chip SRAM
• External port for interfacing to off-chip memory and
• Host port and multiprocessor Interface
• DMA controller
shared data register file
transfers between memory and the core at every core pro-
cessor cycle
peripherals
on Page 1
®
—Super Harvard Architecture Com-
illustrates the following architec-
Speed
0.46 Ps
25 ns
100 ns
150 ns
225 ns
240 Mbytes/s
Table 2
Table
shows perfor-
Rev. F | Page 4 of 64 | March 2008
Cycles
18,221
1
4
6
9
1), a
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-2106x processors
are code- and function-compatible with the ADSP-21020.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general–purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
• Serial ports and link ports
• JTAG Test Access Port
1
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICES
DEVICE
SERIAL
(6 MAX)
SERIAL
DEVICE
CLOCK
LINK
3
4
Figure 2. ADSP-2106x System Sample Configuration
CLKIN
EBOOT
LBOOT
IRQ2–0
FLAG3–0
TIMEXP
LxCLK
LxACK
LxDAT3–0
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID2–0
ADSP-2106x
RESET
DATA47–0
ADDR31–0
DMAG1–2
DMAR1–2
ADRCLK
JTAG
MS3–0
BR1–6
PAGE
REDY
SBTS
BMS
HBG
ACK
HBR
6
WR
RD
CS
PA
DATA
CS
ADDR
DATA
ADDR
DATA
OE
WE
ACK
CS
ADDR
DATA
PROCESSOR
(OPTIONAL)
INTERFACE
DMA DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
MEMORY-
HOST
DEVICES
MAPPED
EPROM
BOOT