SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 162

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
Table 10-5. SPDO_CTL MMIO register
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read, and writ-
ten as ’0’s.
The SPDO_FREQ register determines the frequency of
operation of the DDS, and hence the sample rate of out-
going audio. Refer to
gramming.”
SPDO_BASE1 contains the memory address of DMA
buffer 1. SPDO_BASE2 contains the memory address of
DMA buffer 2. SPDO_SIZE determines the size, in bytes,
of both DMA buffers. Assignment to SPDO_BASE1,
SPDO_BASE2 and SPDO_SIZE have no effect on the
state of the SPDO_STATUS flags; the ACK_BUF1 and
10-6
BUF2_INTEN
HBE_INTEN
UDR_INTEN
SLEEPLESS
LITTLE_ENDIAN
TRANS_MODE
TRANS_ENABLE
RESET
field
and
Section 10.9, “Transparent Mode.”
type
w/o
r/w
r/w
r/w
r/w
r/w
r/w
r/w
PRELIMINARY SPECIFICATION
Section 10.8, “Sample Rate Pro-
If BUF2_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
If HBE asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
If UNDERRUN asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
If ‘1’, the SPDO block does not
power down when PNX1300 goes
into global power-down mode. If ‘0’,
the block does power down.
If asserted, the 32-bit data SPDIF
descriptor word or transparent
mode data word is assembled
using little endian byte ordering,
otherwise big-endian.
• 000 - IEC-958 mode. Hardware
• 010 transparent mode, LSB first.
• 011 transparent mode, MSB
• Any other code reserved for
The transmission mode should only
be changed while transmission is
disabled.
Writing a ‘1’ to this bit enables
transmission per the selected
mode. Writing a ‘0’ here stops any
ongoing transmission after com-
pleting any actions related to the
current data descriptor word.
Writing a ‘1’ to this bit resets the
SPDO unit and should be used with
extreme caution. Ongoing trans-
mission will be interrupted, receiv-
ers may be left in a strange state.
performs bi-phase mark encod-
ing, preamble generation, and
parity generation, and transmits
one IEC-958 subframe for each
data descriptor word.
The 32-bit data descriptor words
are transmitted as is, LSB first.
first. The 32-bit data descriptor
words are transmitted as is,
MSB first.
future extensions.
description
ACK_BUF2 bits signal the assignment of valid data to
the DMA buffers. Any change to the BASE register
should only be done to an inactive buffer and should pre-
cede the ACK to that buffer.
SPDO_TSTAMP is a read-only register containing the
cycle count at which the last bit from the last emptied
buffer was transmitted across the output pin. Refer to
Section 10.13, “Timestamps.”
10.15 RESET
The SPDO block is reset by global PNX1300 reset pin
TRI_RESET# or by writing a ‘1’ to the RESET bit in
SPDO_CTL. The SPDO block is not affected by
DSPCPU reset initiated though the PCI block BIU_CTL
register. Either reset method sets the SPDO block in the
following state:
• SPDO_BASE1, SPDO_BASE2, SPDO_SIZE = 0
• SPDO_STATUS: all defined fields set to ’0’, except
• SPDO_CTL all defined fields set to value 0
The SPDO block timestamp counter is reset by
TRI_RESET# or by DSPCPU reset initiated through
BIU_CTL, so as to ensure that it stays synchronous to
the CCCOUNT DSPCPU register.
10.16 POWER DOWN AND SLEEPLESS
The SPDO block enters powerdown state whenever
PNX1300 is put in global powerdown mode, except if the
SLEEPLESS bit in SPDO_CTL is set. In the latter case,
the block continues DMA operation and will wake up the
DSPCPU whenever an interrupt is generated.
SPDO can be separately powered down by setting a bit
in the BLOCK_POWER_DOWN register. For a descrip-
tion of powerdown, see
ment.”
The SPDO block should not be active when applying glo-
bal powerdown (TRANS_ENABLE = 0), or if active,
SLEEPLESS should be asserted. SPDO should not be
active if powered down separately.
If the block enters power-down state while transmission
is enabled, its operation continues from the interrupted
clock cycle, but the output signal generated by the block
has undergone a pause that is unacceptable to external
equipment.
10.17 HBE AND HIGHWAY LATENCY
The SPDO unit uses one internal 64-byte buffer and two
32-bit holding registers. Under normal operation, the in-
ternal buffer is refilled from SDRAM fast enough to avoid
missing any data, while data is being sent from the two
32-bit registers. If the highway arbiter is set up with an in-
sufficient latency guarantee, the situation can arise in
which the 64-byte buffer is not refilled in time. In that case
the HBE error is raised, and some data has been irrevo-
cably lost. The HBE condition is sticky, and can only be
cleared by an explicit ACK_HBE.
BUF1_ACTIVE = 1
Chapter 21, “Power Manage-
Philips Semiconductors