SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 246

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
15.9.4
This 32-bit register contains the picture layer information
necessary for the VLD to parse the macroblocks within
that picture. Again, the values for each of these fields are
determined by the appropriate standard (MPEG [1-3]).
Table 15-7. VLD picture info register (r/w)
15.10 ERROR HANDLING
Upon encountering a bitstream error, the VLD will set the
bitstream-error flag (ERROR) in the VLD_STATUS reg-
ister and interrupt the DSPCPU, if the interrupt is en-
abled. Note that if a start code is present (in the VLD shift
register) when an error is detected, then both the start
code and the error bits will be set. A separate flush com-
mand is required to flush any valid data in the run-level
and macroblock header output buffers.
The DSPCPU de-asserts the ERROR flags by writing a
‘1’ to the ERROR flag.
15.11 INTERRUPT
The interrupt source number for the VLD is 14 and it
should be set in level sensitive mode (see
3.5.3.6 on page
15-8
PICT_TYPE (picture
type)
PICT_STRUC (picture
structure)
FPFD (frame predic-
tion frame dct)
INTRA_VLC
CONCEAL_MV
reserved
MPEG2 mode
reserved
HFRS (horizontal for-
ward rsize)
VFRS (vertical forward
rsize)
HBRS (horizontal
backward rsize)
VBRS (vertical back-
ward rsize)
Name
VLD Picture Info (VLD_PI)
3-11).
PRELIMINARY SPECIFICATION
(bits)
Size
2
2
1
1
1
6
1
2
4
4
4
4
I, P, or B picture
field or frame picture
specifies that this picture
uses only frame prediction
and frame dct
Use DCT table zero or one
concealment vectors present
in the bitstream
Reserved for future expan-
sion
Switches VLD between
MPEG-1 and MPEG-2
decoding.
Value ‘1’ = MPEG-2 mode
reserved
size of residual motion vector
size of residual motion vector
size of residual motion vector
size of residual motion vector
Description
Section
15.12 RESET
The VLD block is reset by a hardware reset or a software
reset. The hardware reset signal is generated from the
external pin TRI_RESET#. The software reset is initiated
by
VLD_COMMAND register. Refer
tails on the software reset procedure.
Table 15-8. Software reset procedure
15.13 ENDIAN-NESS
VLD supports little-endian and big-endian modes of op-
erations. Refer to
ification of the VLD input and output data.
15.14 POWER DOWN
The VLD block can be separately powered down by set-
ting a bit in the BLOCK_POWER_DOWN register. For a
description of powerdown, see
agement.”
The VLD block should not be active when applying block
powerdown.
If the block enters power-down state while it is enabled,
its behavior upon power-up is undefined.
15.15 REFERENCES
[1] ISO/IEC IS 13818-2, International Standard (1994),
MPEG-2 Video.
[2] ISO/IEC IS 11172-2, International Standard (1992),
MPEG-1 Video.
[3] MPEG Video Compression Standard, by Joan L.
Mitchell, William B. Pennebaker, Chad E. Fogg, Didier J.
LeGall; ITP publication.
i
i to j
j+1
Cycle
no.
writing
DSPCPU issues the ‘Reset
the VLD’ command by writ-
ing the required value in the
VLD_COMMAND register.
VLD will complete the pend-
ing, if any, highway transac-
tions.
VLD will perform the full
reset.
a
Action
Appendix C
‘Reset
Philips Semiconductors
VLD’
for the endian-ness spec-
Chapter 21, “Power Man-
Table 15-8
Any highway transac-
tions, once started, will
not be aborted in the
middle
All status and control
registers are reset and
all the buffers are
made empty.
MMIO Registers initial-
ized to zero includes
VLD_STATUS.
command
Remarks
for the de-
in
the