SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 265

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
17.10.2 SSI Control/Status Register (SSI_CSR)
SSI_CSR is a 32-bit read/write register that controls the SSI unit and shows the current status of the SSI module. The
default value after hardware reset is 0x0000F000.
Table 17-8. SSI control/status register (SSI_CSR) fields
TMS
CDE
CD2
SLP
CTUE
CROE
CFES
CCDS
WAW
WAR
TDE
RDF
TUE
ROE
FES
CDS
RIO1
RIO2
Field
Test Mode Select (Bit 31-30). Value should only be changed when the transmitter and receiver are disabled. See
Table
Change Detector Enable (Bit 29). CDE enables the change detector function on the SSI_IO1 pin. When CDE is set,
the DSPCPU will be interrupted when CDS in the SSI status register is set. When CDE is cleared, this interrupt is
disabled. However, the CDS bit will always indicate the change detector condition.
When the change detector is enabled, the CLK samples SSI_IO1. The CDS bit will be set for either a ‘0’ –> ‘1’ or a ‘1’
–> ‘0’ change between the current value and the stored value.
RXCLK Divider (Bit 28). When CD2 = ‘1’, the internal RxCLK is divided by two. In the divide by 2 mode, the clock edge
that samples the asserted Frame Sync Pulse will resync the RxCLK divider to be a data capture edge. Data samples
will occur every other clock thereafter until the end of the valid slots in the frame.
Sleepless (Bit 27). When set, this bit allows the SSI to ignore the global power down signal. If cleared, assertion of the
global power down signal will cause the SSI transmitter to finish transmission of the current 16-bit word, then enter a
state similar to transmitter disabled, (SSI_CTL.TXE = ’0’).
In the receiver, a 16-bit word currently being transmitted to RxSR will complete reception and be transferred to the
RxFIFO. The receiver will then enter a state similar to receiver disabled, (SSI_CTL.RXE = ‘0’).
Clear Transmitter Underrun Error (Bit 21). A control bit written by the DSPCPU to indicate that the transmitter underrun
error flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.TUE. The bit always reads ‘0’.
Clear Receiver Overrun Error (Bit 20). A control bit written by the DSPCPU to indicate that the receiver overrun error
flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.TOE. The bit always reads ‘0’.
Clear Framing Error Status (Bit 19). A control bit written by the DSPCPU to indicate that the receiver’s framing error
flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.FES. The bit always reads ‘0’.
Clear Change Detector Status (Bit 18). A control bit written by the DSPCPU to indicate that the change detector status
on IO1 flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.CDS. The bit always reads ‘0’.
Word buffers Available for Write (Bit 15-12). The WAW[3:0] bits provide the number of 32-bit words available for write
in the transmit buffer (TxFIFO). The SSI can store 15 words in the transmit FIFO. When the FIFO is empty, WAW =
‘15’. When the FIFO is full, WAW = ‘0’ and the SSI will ignore any further attempts to add words to the FIFO. Note:
The fill routine should check that WAW is nonzero, before writing data.
Word buffers Available for Read (Bit 11-8). The WAR[3:0] bits provide the number of 32-bit word available for read in
the receive buffer (RxFIFO). The SSI can store 16 words in the receive FIFO. However, the maximum value indicated
by the WAR register = ‘15’ (because it’s a 4-bit register field). When the FIFO is empty, WAR = ‘0’. When the FIFO is
full, WAR = ‘15’ and the SSI will generate an overrun error if more data is received.
Transmit Data register Empty (Bit 7). In normal operation, this bit will be set when the number of empty words in the
TxFIFO is greater than the Interrupt Level Select value, SSI_CTL.ILS. If SSI_CTL.TIE is set, the SSI will generate an
interrupt. When set, it indicates that the SSI_TxDR/TxFIFO registers require DSPCPU service for refilling after normal
transmission. As the DSPCPU refills the TxFIFO during the interrupt service routine, this bit will be cleared by the SSI
when the number of empty slots drops below the value of SSI_CTL.ILS.
Receive Data register Full (Bit 6). In normal operation, this bit will be set when the number of words in the RxFIFO is
greater than SSI_CTL.ILS. If SSI_CTL.RIE is set, the SSI will generate an interrupt. When set, this bit indicates that
normal received data resides in SSI_RxDR register and RxFIFO buffer for reading. DSPCPU must service the RxFIFO
before a receiver overrun occurs.
Transmitter Underrun Error (Bit 5). No current data was available from the TxFIFO when a load of the TxSR was
scheduled. The transmitted message may have been corrupted. Generates interrupt if enabled by TIE.
Receive Overrun Error (Bit 4). No RxFIFO slot in which to store received data. These bits have been lost and the mes-
sage stream is incomplete. Generates an interrupt if enabled by RIE.
Frame Error (Bit 3). A frame sync pulse has been detected where not expected or did not occur as expected during
transmit or receive. Received data may be invalid. Transmit data have been sent out of sync. Receive frame error
RXFES generates an interrupt if enabled by RIE. Transmit frame error TXFES generates an interrupt if enabled by TIE
Change Detector Status (Bit 2). The input change detector on SSI_IO1 pin has detected a change in state.
Read IO1 (bit 1). RIO1 reflects the value on the SSI_IO1 pin.
Read IO2 (bit 2). RIO2 reflects the value on the SSI_IO2 pin.
17-9.
PRELIMINARY SPECIFICATION
Description
Synchronous Serial Interface
17-11