SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 228

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
The ICP block can be separately powered down by set-
ting a bit in the BLOCK_POWER_DOWN register. Refer
to
It is recommended that ICP is in an idle state before
block level power down is activated.
14.6.3
The DSPCPU commands the ICP to perform an opera-
tion by loading the DP with a pointer to a parameter
block, loading the MPC with a microprogram start ad-
dress and setting Busy in the SR. For example to cause
the ICP to scale and filter an image, set up a block of
SDRAM with the image and filter parameters, load the
MPC with the starting address of the appropriate micro-
program entry point in SDRAM, load the DP with the ad-
dress of the parameter block, and set Busy in the SR by
writing a ‘1’ to it. When the filter operation is complete,
the ICP will set Done and issue an interrupt. The
DSPCPU clears the interrupt by writing a ‘1’ to
ACK_DONE. Note: The interrupt should be set up as a
‘level triggered.’
When the DSPCPU sets Busy, the MCU begins reading
the microprogram from SDRAM. The microinstructions
are read in from SDRAM as required by the ICP, and in-
ternal pre-fetching is used to eliminate delays. Setting
Busy enables the MCU clock, the first block of microin-
structions is automatically read in, and the MCU begins
instruction execution at the current address in the MPC.
Clearing Busy stops the MCU clock. Busy can be cleared
by hardware reset, by the MCU, or by the DSPCPU.
Hardware reset clears the Status register, including Busy
and Done, and internal registers, such as the TCR.
When the MCU completes a microprogram operation,
the microprogram typically clears Busy and sets Done,
causing an interrupt if IE is enabled.
The DSPCPU performs a software reset by clearing
(writing a ‘0’ to) Busy and by writing a ‘1’ to Reset. The
DSPCPU can also set Done to force a hardware inter-
rupt, if desired.
14.6.4
The ICP comes with a factory-generated microprogram
set which implements the functions of the ICP. The mi-
croprogram set includes the following functions:
1. Loading the filter coefficient RAMs.
2. Horizontal scaling and filtering from SDRAM to
3. Vertical scaling and filtering from SDRAM to SDRAM
4. Horizontal scaling, filtering and YUV to RGB conver-
14-18
Chapter 21, “Power Management.”
SDRAM of an input image to an output image. The in-
put and output images can be of any size and position
that fits in SDRAM. The scaling factors are, in gener-
al, limited only by input and output image sizes.
of an input image to an output image. The input and
output images can be of any size and position that fits
in SDRAM. The scaling factors are, in general, limited
only by input and output image sizes.
sion of an input image from SDRAM to an output im-
age to PCI or SDRAM, with an alpha-blended and
ICP Operation
ICP Microprogram Set
PRELIMINARY SPECIFICATION
The microprogram is supplied with the ICP as part of the
device driver. The entry point in the microprogram de-
fines which ICP operation is to be done. The entry points
are given below in terms of word offsets from the begin-
ning of the microprogram:
14.6.5
The processing time for typical operations on typical pic-
ture sizes has been measured.
Measurements were performed with the following config-
uration:
• CPU clock and SDRAM clock set to 100 MHz
• PCI clock set to 33MHz
• All measurement with PCI as pixel destination were
• TRITON2
• PNX1300 arbiter set to default settings
• PNX1300 latency timer set to maximum value = 0xf8.
• Overlay sizes were the same as picture sizes.
Results are tabulated below for three different cases of
available memory bandwidth:
1. No other load to SDRAM, i.e. full SDRAM bandwidth
available for ICP. See
2. SDRAM memory loaded to 95% of its bandwidth by
DCACHE traffic from DSPCPU. Priority delay = 1, i.e.
ICP did wait one block time before competing for memo-
ry. See
3. SDRAM memory loaded to 95% of its bandwidth by
DCACHE traffic from DSPCPU. Priority delay = 16, i.e.
ICP did wait 16 block times before competing for memo-
ry. See
Note: A load of 95% of the memory bandwidth is very
rarely found in a real system. So the results in these ta-
bles may be useful to estimate upper bounds for the
computation time in a loaded system.
The priority delays were set to the minimum and maxi-
mum possible values, so the computation time for other
priority delay values should be somewhere in between.
chroma-keyed RGB overlay and a bit mask. The input
and output images can be of any size and position
that fit in SDRAM and can be output to the PCI bus or
SDRAM. In general, scaling factors are limited only by
input and output image sizes.
done with an Imagine 128 Series II graphics card,
which never caused a slowdown of the ICP opera-
tion.
SB82371SB based Intel
Offset
0
1
2
3
Table
Table
ICP Processing Time
14-6.
14-7.
mother-board
Function
Load coefficients
Horizontal scaling and filtering
Vertical scaling and filtering
Horizontal scaling, filtering, YUV to RGB
conversion, bit masking (PCI) and over-
lay (PCI) with alpha blending and
chroma keying
Table
Philips Semiconductors
®
14-5.
Pentium™ chipset.
with
SB82437UX
and