SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 260

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
17.5
17.5.1
Write the SSI_CTL to reset and enable the receiver. Both
the transmitter and receiver must be reset simultaneous-
ly. This will set all registers and internal logic the same as
after a power-up reset. The recommended procedure is
to set up all receiver related control bits before perform-
ing a RXE assert. In particular, fields TCP, RSD, IO1,
IO2, FMS, FSP, MOD and TMS should NOT be changed
after enabling the receiver until after the next receiver re-
set.
The direction of shift in the RxSR, mode, and the clock
edge polarity must also be configured in SSI_CTL. Set
the framing controls according to the external communi-
cation circuit’s requirements. Note that the Rx and Tx
machines share the framing and clock divide controls.
If the DSPCPU does not poll the SSI status registers, it
should enable the receiver interrupt and set the ILS field
by writing to the SSI_CTL to allow interrupt driven servic-
ing of the SSI receiver. Note that both transmit and re-
ceive use the same ILS field.
If the RxCLK is double the frequency of the data rate on
the SSI bus, SSI_CSR.CD2 can be used to divide the re-
ceive clock by two.
17.5.2
The
SSI_RxDATA into the RxSR on the first active edge of
SSI_RxCLK received after the receiver is enabled (see
also
ferred to the first available RxFIFO entry and possibly
SSI_RxDR. Reception continues and when RxSR is full
again, a parallel load of the next available RxFIFO entry
from RxSR is accomplished. This continues until the re-
ceiver is disabled or reset. If the receive state machine
must transfer RxSR into one of the RxFIFO entries and
none of the RxFIFO entries is available, the value will be
lost and the receive overrun bit will be set.
17-6
Figure 17-7. The receive buffer operation
Figure
Hiway
To
receive
SSI RECEIVE OPERATION
Setup SSI_CTL
Operation Details
SSI_RxDR
17-7). When full, the RxSR is parallel trans-
state
PRELIMINARY SPECIFICATION
machine
0
rd_ptr
1
2
will
3
begin
4
5
32-depth of 16-bit buffer
shifting
6
7
...
17.5.3
The status of the RxFIFO is visible in SSI_CSR. WAR is
the number of 32-bit words available for read; it is more
than ILS (RDF). As the receive state machine loads
RxFIFO from the RxSR, it sets the associated status bit.
The SSI will generate an internal interrupt when the num-
ber of full entries in RxFIFO is more then SSI_CTL.ILS.
If the receive state machine attempts to load RxFIFO
while none of the RxFIFO entries is available, it will set
the receive overrun bit and generate an interrupt.
Due to the possibility of speculative reading of the
SSI_RxDR, the DSPCPU must explicitly indicate a suc-
cessful read of SSI_RxDR by writing a ‘1’ in the LSB to
the SSI_RxACK register. The status fields of the
SSI_CSR will update within 1 highway clock cycle after
completion of writing to SSI_RXACK register.
17.6
The frame timing can be controlled by the FSS and VSS
fields in the SSI_CTL register.
The FSS[3:0] bits control the divide ratio for the program-
mable frame rate divider used to generate the frame
sync pulses. The valid value ranges from 1 to 16 slots of
16 bit each, e.g. a value of 5 indicates that a frame con-
tains 5 slots of 16 bits each. Note: the value ‘16’ is ac-
complished by storing a ‘0’ in this field. If a codec is con-
nected which generates 6 slots and the SSI block is
programmed to 5 slots a framing error is indicated in
SSI_CSR.FES; and if TIE or RIE is enabled, an interrupt
is generated.
For an example of a frame timing diagram see
Figure 17-11
The VSS[3:0] bits control the number of valid slots in the
frame, starting from slot 1. For example, if the VSB[3:0]
bits are if set to 4 and FSS set to 5, slots 1, 2, 3 and 4 in
the frame contain valid data from the transmitter FIFO
and slot 5 will contain non-valid data. The receiver will
only accept data in slot 1, 2, 3 and 4.
...
FRAME TIMING
...
Interrupt and Status
wr_ptr
...
and
...
Figure
29
17-12.
30
Philips Semiconductors
31
SSI_RxDATA
16-bit