SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 94

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
Figure 5-13. LRU bit definitions; 2_way[k] is the two-way LRU bit of pair k = (j div 2) for set element j.
Figure 5-14. Format of the memory_events MMIO register.
al, n×(n–1)/2 bits for n-way LRU). If set element k is ref-
erenced, the cache sets row k to ‘1’ and column k to ‘0’:
The LRU element is the one for which the entire row is ‘0’
(or empty) and the entire column is ‘1’ (or empty):
For a 4-way set-associative cache, this algorithm re-
quires six bits per set of four cache blocks. On every
cache hit, the LRU info is updated by setting three of the
six bits to ‘0’ or ‘1’, depending on the set element that
was accessed. The bits need only be written, no read-
modify-write is necessary. On a miss, the cache reads
the six LRU bits to determine the replacement block.
PNX1300 combines the two-way and four-way algo-
rithms into an 8-way hierarchical LRU algorithm. A total
of ten administration bits are required: six to maintain the
four-way LRU plus four bits maintain the four two-way
LRUs.
The hierarchical algorithm has performance close to full
eight-way LRU, but it requires far fewer bits—ten instead
of 28 bits—and is much simpler to implement.
To update the LRU bits on a cache hit to element j (with
0 <= j <= 7), the cache applies m = (j div 2) to the four-
way LRU administration and (j mod 2) is applied to the
two-way administration of pair m. To select a replace-
ment victim, the cache first determines the pair p from the
four-way LRU and then retrieves the LRU bit q of pair p.
The overall LRU element is the p×2+q.
5.6.6
Reset causes the LRU administration bits to initialized to
a legal state:
5-12
MMIO_BASE
R[k, 0..n–1] ← 1,
R[0..n–1, k] ← 0
R[k, 0..n–1] = 0 and R[0..n–1, k] = 1
R[1,0] ← R[2,0] ← R[3,0] ← 1
R[2,1] ← R[3,1] ← R[3,2] ← 0
2_way[3] ← 2_way[2] ← 2_way[1] ← 2_way[0] ← 0
0x10 000C
offset:
LRU Initialization
2_way[3]
LRU bit 9
MEM_EVENTS (r/w)
2_way[2]
LRU bit 8
PRELIMINARY SPECIFICATION
2_way[1]
LRU bit 7
31
0
2_way[0]
LRU bit 6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
27
LRU bit 5
R[1,0]
23
LRU bit 4
R[2,1]
5.6.7
The ten LRU bits per set are mapped as shown in
Figure
turned by the special operation rdstatus for the data
cache and a ld32 from MMIO space (see
“Reading Tags and Cache
cache.
5.6.8
For the PNX1300 dual-ported data cache, two memory
operations to the same set are possible in a single clock
cycle. To support this concurrency, two updates of the
LRU bits of a single set must be possible.
The following rules are used by PNX1300:
1. LRU bits that are changed by exactly one port receive
2. LRU bits that are changed by both ports receive a val-
5.7
The caches implement support for performance evalua-
tion. Several events that occur in the caches can be
counted using the PNX1300 timer/counters, by selecting
the source CACHE1 and/or CACHE2, as described in
Section 3.8, “Timers.”
tracked simultaneously by using 2 timers.
The MMIO register MEM_EVENTS determines which
events are counted. See
MEM_EVENTS.
tracked
MEM_EVENTS fields. Event1 selects the actual source
the value according to the algorithm described above.
ue as if the algorithm were first applied for the access
in port zero and then for the access in port one.
19
5-13. This is the format of the LRU field as re-
PERFORMANCE EVALUATION
SUPPORT
LRU bit 3
R[2,0]
and
LRU Bit Definitions
LRU for the Dual-Ported Cache
15
the
Table 5-14
LRU bit 2
R[3,2]
corresponding
Two different events can be
11
Figure 5-14
Philips Semiconductors
LRU bit 1
R[3,1]
lists the events that can be
Status”) for the instruction
7
Event2
LRU bit 0
R[3,0]
values
for the format of
Section 5.4.8,
3
Event1
for
0
the