SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 392

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
Convert signed integer to floating-point with
rounding toward zero
SYNTAX
FUNCTION
DESCRIPTION
and writes the result into rdest. Rounding is performed toward zero; the IEEE rounding mode bits in PCSW are
ignored. This is the preferred rounding mode for ANSI C. If
the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as
a side-effect of any floating-point operation but can only be reset by an explicit
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates
ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 3
r40 = 0xffffffff (-1)
r10 = 0, r50 = 0xfffffffd
r20 = 1, r50 = 0xfffffffd
r60 = 0x7fffffff (2147483647)
r70 = 0x80000000 (-2147483648)
r80 = 0x7ffffff1 (2147483633)
The
The
The
[ IF rguard ] ifloatrz rsrc1 → rdest
if rguard then {
}
rdest ← (float) ((long)rsrc1)
ifloatrz
ifloatrzflags
ifloatrz
Initial Values
operation converts the signed integer value in rsrc1 to single-precision IEEE floating-point format
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
ifloatrz r30 → r100
ifloatrz r40 → r105
IF r10 ifloatrz r50 → r110
IF r20 ifloatrz r50 → r115
ifloatrz r60 → r117
ifloatrz r70 → r120
ifloatrz r80 → r122
Operation
ifloatrz
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r100 ← 0x40400000 (3.0)
r105 ← 0xbf800000 (-1.0)
no change, since guard is false
r115 ← 0xc0400000 (–3.0)
r117 ← 0x4effffff (2.147483520e+9), INX flag set
r120 ← 0xcf000000 (-2.147483648e+9)
r122 ← 0x4effffff (2.147483520e+9), INX flag set
causes an IEEE exception, such as inexact,
writepcsw
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ifloat ufloatrz ifixieee
Result
ifloatflags
ATTRIBUTES
operation. The update of
SEE ALSO
ifloatrz
ifloatrz
falu
117
1, 4
No
—
1
3
A-94
.