SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 523

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
The
various pixel formats used in the ICP unit. Refer to
C-2
ble C-4
in Big Endian mode. No swapping is done in the Little En-
dian mode.
Table C-5. ICP byte swapping type for input data
Table C-6. ICP byte swapping type for output data
The ICP has a byte sex bit (L) defined in its MMIO-based
configuration register. The setting of this bit and the BSX
bit in the PCSW register should be the same. The L bit
must be set by the software.
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Big Endian
Figure C-12. Memory image format for raw 8-bit and 10-bit data
Endian-ness
Endian-
ness
lsb is the Least Significant Byte
msb is the Most Significant Byte
raw 8-bit data
in memory
and
raw 10-bit data
in memory
Table C-5
and
Figure C-10
Table
L bit
0
0
0
0
0
0
0
shows the byte-swap implementation of
L bit
C-5. Byte-swapping is performed only
0
0
0
0
RGB 8A: 233
RGB 8R: 332
RGB 15+α
RGB 16
RGB 24+α
RGB24
packed
YUV- 4:2:2
packed
for the byte-swap code used in
Pixel Type
Y,U,V planar
RGB 24+α
YUV-4:2:2+α
RGB 15+α
Pixel Type
lsb
D
A+3
A+3
n+3
No swap
No swap
BSH
BSH
BSW
No support for Big
Endian
BSH
D
n+1
(see
Big Endian Mode
Figure
D
A+2
Swap Type
A+2
No swap
BSW
BSH
BSH
(see
Figure C-2
n+2
&
msb
Swap Type
Figure
Figure C-2
C-10)
lsb
A+1
D
Figure
A+1
C-10)
n+1
&
Ta-
and A+3 corresponds to byte-3 lane of SDRAM/Hwy
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy
D
n
A+0
A+0
D
C.4.5
The VI unit stores the YUV pixels in planar 4:2:2 or 4:2:0
image format as shown in
8- and 10-bit data as shown in
The VO unit uses YUV-4:2:2 planar, YUV-4:2:0 planar,
and YUV-4:2:2+α packed as input pixel formats. The pla-
nar memory image format of the YUV-4:2:2 and YUV-
4:2:0 are shown in
ry image format for overlay is pictured in
The VI and VO units have a byte-sex bit (Little Endian
and LTL_END) defined in the control MMIO registers,
VI_CONTROL and VO_CONTROL. The definition of
these byte-sex bits and the BSX bit in the PCSW register
should be treated as same. Little Endian and LTL_END
bits must be set by software.
C.4.6
The AI unit uses 8-bit mono, 8-bit stereo, 16-bit mono
and 16-bit stereo data. The AO unit uses 16-bit mono,
16-bit stereo, 32-bit mono and 32-bit stereo data. The
SPDO unit uses 32-bit word data. The memory image
format of these data is presented in
Swapping takes place at the byte level and the bits within
a byte are never disturbed. Both the AI and AO units
have a byte sex bit (LITTLE_ENDIAN) defined in each
units MMIO-based configuration register. The definition
of the these bits and the BSX bit in the PCSW register
should be treated as same. This byte sex bit must be set
by the software.
C.4.7
The VLD inputs data from SDRAM in the form of a bit-
stream with a byte-aligned starting address and outputs
a header stream and a ‘run-level’ data stream. The VLD
unit has a byte sex bit (LITTLE_ENDIAN) defined in its
MMIO-based configuration register. The definition of this
PRELIMINARY SPECIFICATION
n
msb
Video In (VI) and Video Out (VO) Units
Audio In (AI), Audio-Out (AO), and
SPDIF Out (SDO) Units
Variable Length Encoder (VLD) Unit
msb
D
A+3
A+3
n+3
Figure
D
n+1
Little Endian Mode
A+2
A+2
D
C-3. The YUV-4:2:2+α memo-
Figure C-3
n+2
lsb
Figure
msb
A+1
D
A+1
n+1
Figure
and stores the raw
C-12.
D
Endian-ness
Figure
n
C-13.
A+0
A+0
D
n
lsb
C-6.
C-7