SLXT332QE.G2 Cortina Systems Inc, SLXT332QE.G2 Datasheet - Page 20

• Manufacturer Part Number: SLXT332QE.G2
• Manufacturer: Cortina Systems Inc

Specifications of SLXT332QE.G2

• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT332
Datasheet
249075, Revision 2.0
26 June 2007
4.4
4.5
4.6
4.7
Cortina Systems
Jitter Attenuation
A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) provides jitter
attenuation. The JAL is internal and requires no external crystal nor high-frequency
(higher than line rate) clock. When JASEL = 1, the JAL is placed in the receive path.
When JASEL = 0, the JAL is placed in the transmit path. With JASEL clocked by MCLK,
the JAL is disabled. MCLK is the reference for the JAL.
The ES is a 32 x 2-bit register. Data is clocked into the ES with the associated clock signal
(TCLK or RCLK), and clocked out of the ES with the dejittered JAL clock. When the ES is
within two bits of overflowing or underflowing, the ES adjusts the output clock by
bit period. The ES produces an average delay of 16 bits in the associated path.
Host mode provides a dejittered High Frequency Clock (HFC). This 8x clock (12.352 MHz
for T1, 16.384 MHz for E1) is tied to the output clock from the JAL. With JA active in the
receive path, HFC is tied to RCLK, and under LOS conditions, defaults to MCLK. With JA
active in the transmit path, HFC is tied to TCLK, and defaults to MCLK if TCLK is not
available. If the JA is disabled, HFC is tied to MCLK.
Built
In Host mode, the LXT332 provides for Built-In Self Test (BIST) applications.
Quasi-Random Signal Source (QRSS) generation and detection circuitry is integrated into
the LXT332. When the QRSS function is selected, the LXT332 detects and reports QRSS
pattern sync on the incoming signal. When triggered, the LXT332 also transmits the
QRSS pattern onto the line. Pattern transmission and detection is independently triggered
and reported for each port. Refer to
for detailed description.
Operating Modes
The LXT332 transceiver operates in either stand-alone Hardware (default) mode or Host
mode depending on the input to the SPE pin.
The data I/O mode (bipolar or unipolar) is controlled by the TRSTE pin. When TRSTE is
Low, Bipolar I/O mode is selected. When TRSTE is clocked, Unipolar I/O is selected.
Several diagnostic modes are available on command.
Host Mode Control
The LXT332 operates in the Host mode when the SPE pin is clocked with MCLK. In Host
mode a microprocessor controls the LXT332 through the serial I/O port (SIO) which
provides common access to both LIUs. Each of the two LIUs contains a pair of data
registers, one for command inputs and one for status outputs. Only one LIU can be
selected at a time. If both PS0 and PS1 are active, Port 0 has priority over Port 1. An SIO
transaction is initiated by a falling pulse on one of the two Port Select pins, PS0 or PS1. A
High-to-Low transition on PS0/1 is required for each subsequent access to the Host mode
registers. If both PS0 and PS1 are active simultaneously, Port 0 has priority over Port 1.
The LIU, selected by the PS pulse, responds by writing the incoming serial word from the
SDI pin into its command register.
serial word consists of an 8-bit Command/Address byte and an 8-bit Data byte. If the
command word contains a read request, the addressed LIU subsequently outputs the
contents of its status register onto the SDO pin.
®
LXT332 Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
-
In Self Test
Figure 5
Section 4.9, Diagnostic Mode Operation, on page 25
shows an SIO write operation. The 16-bit
Figure 6
shows an SIO read operation.
4.4 Jitter Attenuation
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