SLXT970AQC.B11-831643

Manufacturer Part NumberSLXT970AQC.B11-831643
ManufacturerCortina Systems Inc
SLXT970AQC.B11-831643 datasheet
 


Specifications of SLXT970AQC.B11-831643

Number Of Receivers1Data Rate10/100Mbps
Operating Supply Voltage (typ)5VOperating Temperature ClassificationCommercial
Operating Supply Voltage (max)5.25VOperating Supply Voltage (min)4.75V
MountingSurface MountPin Count64
Operating Temperature (max)70COperating Temperature (min)0C
Lead Free Status / RoHS StatusNot Compliant  
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®
Intel
LXT970A Dual-Speed Fast
Ethernet Transceiver
®
The Intel
LXT970A Dual-Speed Fast Ethernet Transceiver (called hereafter the LXT970A
Transceiver) is an enhanced derivative of the Intel
Transceiver that supports selectable driver strength capabilities and link-loss criteria. The
LXT970A Transceiver supports 100BASE-TX, 10BASE-T, and 100BASE-FX applications. It
provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access
Controllers (MAC)s and a pseudo-ECL interface for use with 100BASE-FX fiber networks.
The LXT970A Transceiver supports full-duplex operation at 10 and 100 Mbps. Its operating
condition is set using auto-negotiation, parallel detection or manual control. The encoder may be
bypassed for symbol mode applications.
The LXT970A Transceiver is fabricated with an advanced CMOS process and requires only a
single 5V power supply. The MII may be operated independently with either a 5V or a 3.3V
supply.
Applications
Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs)
10/100 Switches, 10/100 Printservers
Product Features
IEEE 802.3 Compliant:
— 10BASE-T and 100BASE-TX using a
single RJ-45 connection.
— Supports auto-negotiation and parallel
detection for legacy systems.
— MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber optic capable.
Standard CSMA/CD or full-duplex
operation.
Configurable via MII serial port or external
control pins.
.
Datasheet
®
LXT970 10/100 Mbps Fast Ethernet PHY
100BASE-FX Network Interface Cards
(NICs)
Configurable for DTE or switch
applications.
CMOS process with single 5Vsupply
operation
with provision for interface to 3.3V MII
bus.
Integrated LED drivers.
Integrated supply monitor and line
disconnect during low supply fault.
Available in:
— 64-pin TQFP:
FALXT970ATC Transceiver
JALXT970ATC Transceiver (RoHS-
Compliant)
— 64-pin PQFP:
SLXT970AQC Transceiver
EGLXT970AQC Transceiveer (RoHS-
Compliant)
Commercial temperature range (0 - 70
ambient).
Order Number: 249099-002
25-Nov-2005
o
C

SLXT970AQC.B11-831643 Summary of contents

  • Page 1

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver ® The Intel LXT970A Dual-Speed Fast Ethernet Transceiver (called hereafter the LXT970A Transceiver enhanced derivative of the Intel Transceiver that supports selectable driver strength capabilities and link-loss criteria. The LXT970A Transceiver ...

  • Page 2

    INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE ...

  • Page 3

    Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Introduction.......................................................................................................... 18 2.2 Interfaces (Network Media/Protocol Support) ..................................................... 19 2.2.1 Twisted-Pair Interface ............................................................................ 19 2.2.2 Fiber Interface ........................................................................................ 19 2.2.3 MII Interface ........................................................................................... 20 2.2.3.1 Selectable Driver Levels............................................................ 20 ...

  • Page 4

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.8.2.2 10T Link Test............................................................................. 38 2.8.2.3 Carrier Sense (CRS) ................................................................. 39 2.8.3 Twisted-Pair PMD Layer ........................................................................ 39 2.8.3.1 Scrambler/Descrambler (100TX Only) ...................................... 39 2.8.3.2 Baseline Wander Correction 2.8.3.3 Polarity Correction..................................................................... 39 2.8.4 Fiber ...

  • Page 5

    Figures 1 Block Diagram ....................................................................................................... 9 2 Pin Assignments .................................................................................................10 3 Network Interface Card (NIC) Application .......................................................... 18 4 MII Interface ....................................................................................................... 20 5 MII Data Interface ............................................................................................... 21 6 Loopback Paths .................................................................................................. 23 7 Repeater Block Diagram .................................................................................... 24 ...

  • Page 6

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Tables 1 Power Supply Signal Descriptions ...................................................................... 10 2 MII Signal Descriptions ....................................................................................... 11 3 Fiber Interface Signal Descriptions ..................................................................... 12 4 Twisted-Pair Interface Signal Descriptions ......................................................... 13 5 LED Indicator Signal Descriptions....................................................................... ...

  • Page 7

    Auto Negotiation Link Partner Ability Register (Address 5) .................................68 51 Auto Negotiation Expansion (Address 6) ............................................................ 69 52 Mirror Register (Address 16, Hex 10)..................................................................69 53 Interrupt Enable Register (Address 17, Hex 11) ................................................. 70 54 Interrupt Status Register (Address ...

  • Page 8

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Revision History Revision Date 002 25-Nov-2005 001 January 2001 8 Description Modified Figure 2 “Pin Assignments” on page Added Section 6.1, “Top Label Markings” on page Added Table 57 “Product Information” on page ...

  • Page 9

    Figure 1. Block Diagram TX_EN MII TX_ER TX TXD<0:4> TX_CLK MF<0:4> CFG<0:1> Hardware FDE Interface Management/ TRSTE Mode Select RESET FDS/MDINT MII MDIO MGMT MDDIS MDC Crystal Osc XTALI/O 2 RX_CLK RXD<0:4> MII RX CRS Carrier Sense Collision Detect COL ...

  • Page 10

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 1.0 Pin Assignments and Signal Descriptions Figure 2. Pin Assignments CRS 1 FDS/MDINT 2 TRSTE 3 MF4 4 MF3 5 MF2 6 MF1 7 MF0 8 VCCD 9 FPO # TEST 10 XO ...

  • Page 11

    Table 2. MII Signal Descriptions (Sheet Pin# Pin Name I/O 63 TXD4 62 TXD3 61 TXD2 60 TXD1 59 TXD0 58 TX_EN 57 TX_CLK 56 TX_ER 46 RXD4 47 RXD3 48 RXD2 49 RXD1 50 RXD0 ...

  • Page 12

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 2. MII Signal Descriptions (Continued) (Sheet Pin# Pin Name 3 TRSTE 15 MDDIS 45 MDC 44 MDIO 2 FDS/MDINT 1. Pin numbers apply to all package types. 2. ...

  • Page 13

    Table 4. Twisted-Pair Interface Signal Descriptions 1 2 Pin# Pin Name I/O 21 TPOP Twisted-Pair Output, Positive and Negative. Differential driver pair produces 802.3- AO compliant pulses for either 100BASE-TX or 10BASE-T transmission. 23 TPON 20 TREF AO Transmit Reference. ...

  • Page 14

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 7. Hardware Control Interface Signal Descriptions (Sheet Pin# Pin Name I/O Multi-Function (MF). Five dual-function configuration inputs. Each pin accepts one of four input voltage levels (V ...

  • Page 15

    Table 7. Hardware Control Interface Signal Descriptions (Continued) (Sheet Pin# Pin Name I/O Full-Duplex Enable. When A/N is enabled, FDE determines full-duplex advertisement capability in combination with MF4 and CFG1. 13 FDE I When A/N ...

  • Page 16

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 8 summarizes the relationship between input voltage levels (V the configuration function for each of the MF input pins. Each MF pin shows two configuration inputs; configuration function and MII address. The ...

  • Page 17

    Table 9. Auto-Negotiation Operating Speed/Full-Duplex Advertisement Settings Desired Configuration Advertise all capabilities Ignore FDE Advertise 10 Mbps only Advertise FD Advertise 10 Mbps only Do Not Advertise FD Advertise 100 Mbps only Advertised FD Advertise 100 Mbps only Do Not ...

  • Page 18

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.0 Functional Description 2.1 Introduction The LXT970A Transceiver, a new-generation version of the LXT970 10/100 PHY Fast Ethernet Transceiver incorporates several functional enhancements for a more robust Ethernet solution. The LXT970A Transceiver supports ...

  • Page 19

    Interfaces (Network Media/Protocol Support) The LXT970A Transceiver provides the following interfaces: • A Twisted-Pair Interface which directly supports 100BASE-TX and 10BASE-T applications. • A pseudo-ECL (PECL) Fiber Interface which supports 100BASE-FX applications through an external fiber transceiver. • An ...

  • Page 20

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver The LXT970A Transceiver does not support the Signal Detect Function. However, the PMA functions of the LXT970A Transceiver guarantee that it will detect invalid link conditions and break down a link, even without ...

  • Page 21

    MII Data Interface Figure 5 shows the data portion of the MII interface. Separate channels are provided for transmitting data from the MAC to the LXT970A Transceiver (TXD), and for receiving data (RXD) from the line. Each channel has ...

  • Page 22

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver The LXT970A Transceiver synchronizes the receive data and control signals to RX_CLK. The LXT970A Transceiver always changes these signals on the falling edge of RX_CLK in order to stabilize the signals at the ...

  • Page 23

    Test Loopback A test loopback function is provided for diagnostic testing of the LXT970A Transceiver. During test loopback the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the LXT970A Transceiver and returned to the ...

  • Page 24

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.2.3.3 Repeater Mode The LXT970A Transceiver MII normally operates in DTE Mode (19.13 = 0). An alternative operating mode is available for repeater applications (19.13 = 1). In Repeater Mode, the Carrier Sense ...

  • Page 25

    The physical interface consists of a data line (MDIO) and clock line (MDC), a control line (MDDIS) and an optional interrupt line (MDINT). The LXT970A Transceiver can signal an interrupt using the MDIO signal as shown in this function. ...

  • Page 26

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 10. Management Interface - Write Frame Structure MDC MDIO 32 "1" (Write) Idle Preamble SFD Op Code 2.2.4 Hardware Control Interface The Hardware Control Interface consists of MF<4:0>, CFG ...

  • Page 27

    Table 13. Operating Configurations / Auto-Negotiation Enabled (Sheet Desired 1,2 Configuration Advertise 10 HD/ Advertise 10/100 Advertise 10/100 HD/ Refer to Table 12 for basic configurations. 2. Refer to ...

  • Page 28

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.3.2 Reference Clock Requirements The LXT970A Transceiver requires a continuous, stable reference clock. There are two clock modes, Master Clock Mode and Slave Clock Mode. Depending on the mode of operation, the clock ...

  • Page 29

    MHz or 2.5 MHz. Either frequency can be used during auto-negotiation. However, once link is established, the supplied frequency must match the link state MHz clock must be supplied for correct operation of a 100TX or 100FX link, ...

  • Page 30

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Interface or MDIO Interface) for operating instructions. Both control modes allow the user to either force the LXT970A Transceiver to a specific configuration or allow it to auto-negotiate the optimum configuration with its ...

  • Page 31

    If the link partner is not capable of auto-negotiation, it transmits either 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. When the LXT970A Transceiver detects either NLPs or Idle symbols, it automatically configures to match the detected ...

  • Page 32

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Refer to the Register Definition section on 2.5.2 Monitoring Status via Indicator Pins The LEDS, LEDR, LEDT, LEDL, and LEDC pins are CMOS digital outputs that drive LEDs. These pins along with the ...

  • Page 33

    In some applications it may be desirable to bypass the 4B/5B encoder/decoder circuit, and operate the MII as a 5-bit symbol mode interface. The LXT970A Transceiver provides additional lines in both the receive and transmit channels (RXD4 & TXD4) to ...

  • Page 34

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 17. 4B/5B Coding 4B Code Code Type ...

  • Page 35

    Operation 2.7.1 10BASE-T MII Operations The MAC transmits data to the LXT970A Transceiver over the MII interface. The LXT970A Transceiver converts the digital data from the MAC into an analog waveform that is transmitted to the network via ...

  • Page 36

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.8.1.1 100X Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter or SSD, for the first two nibbles received across ...

  • Page 37

    Collision Indication Figure 18 shows normal transmission. The LXT970A Transceiver detects a collision if transmit and receive are active at the same time. As shown in COL output is asserted and remains asserted for the duration of the collision. ...

  • Page 38

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 2.8.1.5 SQE (10T Only) When the SQE (heartbeat) function is enabled, the LXT970A Transceiver asserts its COL output for 5-15 BT after each packet. By default, the SQE function is disabled on the ...

  • Page 39

    Carrier Sense (CRS) For 100TX and 100FX links, a start-of-stream delimiter or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes deassertion of CRS. The PMA layer also de-asserts CRS if ...

  • Page 40

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 100 Mbps and is intended for 100FX applications. It does not support 10FL applications. The fiber interface does not support the signal detect function supplied by most fiber optic transceivers. However, the link ...

  • Page 41

    Application Information 3.1 Magnetics Information The LXT970A Transceiver requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 18 for magnetics requirements. A cross-reference list of magnetic manufacturers and part numbers is available in ...

  • Page 42

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 3.3 Design Recommendations The LXT970A Transceiver is designed in accordance with IEEE requirements and provides outstanding receive Bit Error Ratio (BER) and long-line-length performance. Lab tests show that the LXT970A Transceiver performs well ...

  • Page 43

    The recommended implementation is to divide the VCC plane into two sections. The digital section supplies power to the digital VCC pin, VCCIO pin, and to the external components. The analog section supplies power to VCCA, VCCT, and VCCR pins ...

  • Page 44

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver 3.3.5.2 Fiber The fiber interface consists of a pseudo-ECL transmit and receive pair to an external fiber optic transceiver. The transmit pair should be AC-coupled to the transceiver, and biased to 3.7V with ...

  • Page 45

    Typical Application Figure 21 on page 46 groups similar pins; it does not portray the actual chip pinout. The Media Independent Interface (MII) pins are at the upper left. Hardware Control Interface pins are center left. The line interface ...

  • Page 46

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 21. Typical Interface Circuitry GNDD C1 TX_EN TXD<4:0> TX_ER 55Ω TX_CLK 55Ω MII COL 55Ω Data RX_DV I/F 55Ω RX_ER 55Ω RX_CLK 7 55Ω RXD<4:0> TRSTE 55Ω CRS MII MDIO Control FDS/MDINT ...

  • Page 47

    Test Specifications Note: Table 21 through Table 43 specifications of the LXT970A Transceiver. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in apply over the recommended operating conditions specified in Table ...

  • Page 48

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 23. Digital I/O Characteristics Parameter 3 Input Low Voltage 3 Input High Voltage Input Current Output Low Voltage Output High Voltage (MII only) Output High Voltage MII Driver Output Resistance (Line Driver ...

  • Page 49

    Table 26. Low Voltage Fault Detect Characteristics Parameter Detect Fault Threshold Clear Fault Threshold 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 27. 100BASE-TX Transceiver Characteristics ...

  • Page 50

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 29. 10BASE-T Transceiver Characteristics Parameter Peak Differential Output Voltage Transmit Timing Jitter added by the 2,3 MAU and PLS Sections 2 Receive Input Impedance Differential Squelch Threshold 1. Typical values are at ...

  • Page 51

    Figure 22. MII - 100BASE-TX Receive Timing / 4B Mode TPIP CRS 1 TRSTE RX_DV RXD<3:0> RX_CLK COL Table 31. MII - 100BASE-TX Receive Timing Parameters / 4B Mode Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER ...

  • Page 52

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 23. MII - 100BASE-TX Transmit Timing / 4B Mode 0ns TXCL K TX_E N TXD<3:0> TPOP CR S Table 32. MII - 100BASE-TX Transmit Timing Parameters / 4B Mode Parameter TXD<3:0>, TX_EN, ...

  • Page 53

    Figure 24. MII - 100BASE-TX Receive Timing / 5B Mode < > R ...

  • Page 54

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 25. 100BASE-TX Transmit Timing / 5B Mode 0ns TXCL K TX_E N TXD<3:0> TPOP CR S Table 34. MII - 100BASE-TX Transmit Timing Parameters / 5B Mode Parameter TXD, TX_EN, TX_ER Setup ...

  • Page 55

    Figure 26. MII - 100BASE-FX Receive Timing / 4B Mode 0ns FIBIP TRSTE RX_D V RXD<3:0> RX_CLK These parameters apply only when the device is operated in Repeater Mode Repeater Mode, application ...

  • Page 56

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 27. MII - 100BASE-FX Transmit Timing / 4B Mode 0ns TXCL K TX_E N TXD<3:0> FIBOP CR S Table 36. MII - 100BASE-FX Transmit Timing Parameters / 4B Mode Parameter TXD<3:0>, TX_EN, ...

  • Page 57

    Figure 28. MII - 10BASE-T Receiving Timing RX_CLK RXD, RX_DV, RX_ER CRS t 7F TPI t 7H COL Table 37. MII - 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK ...

  • Page 58

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 29. MII - 10BASE-T Transmit Timing TX_CLK t 8A TXD, TX_EN, TX_ER t 8C CRS TPO Table 38. MII - 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High ...

  • Page 59

    Figure 30. 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN COL Table 39. 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only; ...

  • Page 60

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 32. Auto Negotiation and Fast Link Pulse Timing Clock Pulse TPOP t1 Figure 33. Fast Link Pulse Timing FLP Burst TPOP t4 Table 41. Auto Negotiation and Fast Link Pulse Timing Parameters ...

  • Page 61

    Figure 34. MDIO Timing when Sourced by STA MDC MDIO Figure 35. MDIO Timing when Sourced by PHY MDC MDIO Table 42. MDIO Timing Parameters Parameter MDIO Setup before MDC MDIO Hold after MDC MDC to MDIO Output delay 1. ...

  • Page 62

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 36. Power-Down Recovery Timing (Over Recommended Range) VCC RESET MDIO,etc Table 43. Power-Down Recovery Timing Parameters Parameter Power-Down recovery time Hardware reset time 1. Typical values are at 25° C and are ...

  • Page 63

    Register Definitions The LXT970A Transceiver register set includes a total of twelve 16-bit registers. Refer to for a complete register listing. • Seven base registers (0 through 6) are defined in accordance with the “Reconciliation Sublayer and Media Independent ...

  • Page 64

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 45. Control Register (Address 0) Bit Name 1 = Reset chip. 0.15 Reset 0 = Enable normal operation Enable loopback mode. When Loopback is enabled, during 100 Mbps operation, the ...

  • Page 65

    Table 46. Status Register (Address 1) Bit Name 1.15 100BASE-T4 Not Supported. 100BASE-X 1. LXT970A Transceiver able to perform full-duplex 100BASE-X. full-duplex 100BASE-X 1. LXT970A Transceiver able to perform half-duplex 100BASE-X. half-duplex 10 Mb/s 1.12 1 ...

  • Page 66

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 47. PHY Identification Register 1 (Address 2) Bit Name PHY ID 2.15:0 The PHY identifier composed of bits 3 through 18 of the OUI. Number Read Only Table 48. ...

  • Page 67

    Table 49. Auto Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page Not Supported 4.14 Reserved Ignore on read Remote fault. 4.13 Remote Fault remote fault. 4.12:11 Reserved Ignore on read Pause ...

  • Page 68

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 50. Auto Negotiation Link Partner Ability Register (Address 5) Bit Name 1 = Link Partner has ability to send multiple pages. 5.15 Next Page 0 = Link Partner has no ability to ...

  • Page 69

    Table 51. Auto Negotiation Expansion (Address 6) Bit Name 6.15:5 Reserved Ignore Parallel detection fault has occurred. Parallel 6.4 Detection Fault 0 = Parallel detection fault has not occurred Link partner is next page able. Link ...

  • Page 70

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 53. Interrupt Enable Register (Address 17, Hex 11) Bit Name 17.15:4 Reserved Write as 0; ignore on read Reduced MII driver levels. Pull-down strength of the MII driver is reduced ...

  • Page 71

    Table 55. Configuration Register (Address 19, Hex 13) (Sheet Bit Name 19.15 Reserved Write as 0; ignore on read 100BASE-T transmit test enabled, LXT970A Transceiver transmits data regardless of link status. This function is the ...

  • Page 72

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Table 55. Configuration Register (Address 19, Hex 13) (Continued) (Sheet Bit Name 1 = Enable 100BASE fiber interface. 19.2 100BASE- Enable 100BASE twisted-pair interface. 19.1 Reserved Write as ...

  • Page 73

    Mechanical Specifications Figure 38. 64-Pin QFP Package Diagram 64-Pin Quad Flat Pack • Part Number - LXT970AQC • Commercial Temperature Range (0 to +70º Datasheet ® Intel ...

  • Page 74

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 39. 64-Pin TQFP Package Diagram 64-Pin Thin Quad Flat Pack • Part Number - LXT970ATC • Commercial Temperature Range (0 to +70ºC) Millimeters Dim Min A – 0.95 ...

  • Page 75

    Top Label Markings Figure 40 shows a sample TQFP package for the LXT970ATC Transceiver. Note: In contrast to the Pb-Free (RoHS-compliant) TQFP package, the non-RoHS-compliant packages do not have the “e3” symbol in the last line of the package ...

  • Page 76

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 42 shows a sample PQFP package for the LXT970AQC Transceiver. Figure 42. Sample PQFP Package – Intel Pin 1 Figure 43 shows a Pb-Free (RoHS-Compliant) PQFP package for the LXT970AQC Transceiver. Figure ...

  • Page 77

    ... Ordering Information Table 57 lists the LXT970A Transceiver product ordering information. ordering information matrix. Table 57. Product Information Intel Number FALXT970ATC.B11 JALXT970ATC.B11 SLXT970AQC.B11 EGLXT970AQC.B11 Datasheet ® Intel LXT970A Dual-Speed Fast Ethernet Transceiver Revision Package Type Pin Count B11 TQFP B11 TQFP B11 ...

  • Page 78

    Intel LXT970A Dual-Speed Fast Ethernet Transceiver Figure 44 shows an order matrix with sample information for the LXT970A Transceiver. Figure 44. Ordering Information Matrix – Sample S LXT 78 970A Q C B11 Product Revision Alphanumeric ...