PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 112

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-47:
Legend:
Note
9260
9270
9280
9290
92A0
92B0
92C0
92D0
9300
9310
9320
1:
2:
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
EMACx
MCMD
MWTD
MCFG
MADR
MRDD
SA0
SA1
SA2
SUPP
TEST
MIND
(2)
(2)
(2)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
INV Registers”
Reset values default to the factory programmed value.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
RESET
MGMT
31/15
for more information.
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
STNADDR6<7:0>
STNADDR4<7:0>
STNADDR2<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RESET
27/11
RMII
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PHYADDR<4:0>
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPEED
24/8
RMII
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MWTD<15:0>
MRDD<15:0>
Bits
23/7
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(CONTINUED)
21/5
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
STNADDR5<7:0>
STNADDR3<7:0>
STNADDR1<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKSEL<3:0>
LINKFAIL
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REGADDR<4:0>
NOTVALID
TESTBP
18/2
—
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—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and
TESTPAUSE SHRTQNTA
NOPRE
SCAN
SCAN
17/1
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—
—
—
—
—
—
—
MIIMBUSY
SCANINC
READ
16/0
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—
—
—
—
—
—
—
—
—
0000
1000
0000
0000
0000
0020
0000
0000
0000
0100
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
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