PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 64

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-4:
Legend:
Note
10D0
10E0
10F0
1100
1110
1120
1130
1140
1150
1:
2:
IPC10
IPC11
IPC12
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
This bit is unimplemented on PIC32MX764F128H device.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
—
—
DMA7IP<2:0>
DMA5IP<2:0>
CAN2IP<2:0>
(1)
CMP1IP<2:0>
RTCCIP<2:0>
DMA3IP<2:0>
DMA1IP<2:0>
INT4IP<2:0>
I2C1IP<2:0>
SPI2IP<2:0>
I2C4IP<2:0>
USBIP<2:0>
AD1IP<2:0>
IC4IP<2:0>
IC5IP<2:0>
U3IP<2:0>
U5IP<2:0>
U4IP<2:0>
(CONTINUED)
27/11
—
—
(2)
(2)
(2)
26/10
—
—
25/9
DMA7IS<1:0>
DMA5IS<1:0>
CAN2IS<1:0>
—
—
CMP1IS<1:0>
RTCCIS<1:0>
DMA3IS<1:0>
DMA1IS<1:0>
INT4IS<1:0>
I2C1IS<1:0>
SPI2IS<1:0>
I2C4IS<1:0>
AD1IS<1:0>
USBIS<1:0>
IC4IS<1:0>
IC5IS<1:0>
U3IS<1:0>
U5IS<1:0>
U4IS<1:0>
24/8
—
—
(2)
(2)
(2)
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
Section 12.1.1 “CLR, SET and INV Registers”
DMA6IP<2:0>
DMA4IP<2:0>
CMP2IP<2:0>
FSCMIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
CAN1IP<2:0>
OC4IP<2:0>
OC5IP<2:0>
SPI3IP<2:0>
I2C3IP<2:0>
PMPIP<2:0>
SPI4IP<2:0>
I2C5IP<2:0>
FCEIP<2:0>
ETHIP<2:0>
CNIP<2:0>
U1IP<2:0>
U2IP<2:0>
U6IP<2:0>
T4IP<2:0>
T5IP<2:0>
19/3
(2)
(2)
18/2
17/1
DMA6IS<1:0>
DMA4IS<1:0>
CMP2IS<1:0>
FSCMIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
CAN1IS<1:0>
OC4IS<1:0>
OC5IS<1:0>
SPI3IS<1:0>
I2C3IS<1:0>
PMPIS<1:0>
SPI4IS<1:0>
I2C5IS<1:0>
FCEIS<1:0>
ETHIS<1:0>
CNIS<1:0>
U1IS<1:0>
U2IS<1:0>
U6IS<1:0>
T4IS<1:0>
T5IS<1:0>
16/0
for more
(2)
(2)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000