PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 153

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.0
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
FIGURE 24-1:
© 2010 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
ETHERNET CONTROLLER
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS61155) in the “PIC32
Family Reference Manual” , which is
available from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Ethernet Controller
ETHERNET CONTROLLER BLOCK DIAGRAM
RX Bus
TX Bus
Master
Registers
Master
Control
DMA
TX DMA
RX DMA
TX Flow Control
Checksum
RX Filter
Host IF
Ethernet DMA
in
TX BM
RX BM
PIC32MX5XX/6XX/7XX
Following are some of the key features of this module:
• Supports 10/100 Mbps data transfer rates
• Supports full-duplex and half-duplex operation
• Supports RMII and MII PHY interface
• Supports MIIM PHY management interface
• Supports both manual and automatic flow control
• RAM descriptor-based DMA operation for both
• Fully configurable interrupts
• Configurable receive packet filtering
• Supports packet payload checksum calculation
• Supports various hardware statistics counters
Figure 24-1
controller.
receive and transmit path
- CRC check
- 64-byte pattern match
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
TX Function
RX Function
RX Flow
Control
illustrates a block diagram of the Ethernet
Configuration
MAC Control
MAC
Registers
and
MII/RMII
MIIM
IF
IF
DS61156F-page 153
External
PHY