PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 91

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-22:
TABLE 4-23:
Legend:
Note
Legend:
Note
F400 NVMCON
F410
F420 NVMADDR
F430 NVMDATA
F440
F000 OSCCON
F010
0000 WDTCON
F600
F610 RSWRST
F230
1:
1:
OSCTUN
SYSKEY
NVMKEY
NVMSRC
2:
RCON
ADDR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
FLASH CONTROLLER REGISTER MAP
SYSTEM CONTROL REGISTER MAP
31/15
31/15
ON
—
—
—
—
—
—
—
—
—
WR
—
30/14
WREN
30/14
—
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
WRERR
29/13
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
LVDERR
28/12
28/12
—
—
—
—
—
—
—
—
—
LVDSTAT
27/11
27/11
—
—
—
—
—
—
—
—
—
—
(1,2)
26/10
26/10
—
—
—
—
—
—
—
—
—
—
FRCDIV<2:0>
NOSC<2:0>
CMR
25/9
25/9
—
—
—
—
—
—
—
—
—
NVMSRCADDR<31:0>
VREGS
NVMADDR<31:0>
24/8
NVMDATA<31:0>
SYSKEY<31:0>
NVMKEY<31:0>
24/8
—
—
—
—
—
—
—
—
—
Bits
Bits
CLKLOCK
EXTR
23/7
23/7
—
—
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
22/6
SWR
22/6
—
—
—
—
—
—
—
—
SLOCK
21/5
21/5
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
20/4
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
PBDIV<1:0>
SLEEP
19/3
19/3
CF
—
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
18/2
—
—
—
—
—
—
NVMOP<3:0>
PLLMULT<2:0>
SOSCEN
for more information.
17/1
17/1
BOR
—
—
—
—
—
—
—
WDTCLR 0000
OSWEN
SWRST
16/0
16/0
POR
for more
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000