PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 123

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0
FIGURE 9-1:
© 2010 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
PREFETCH CACHE
CTRL
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32 Family
Reference Manual”, which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Prefetch Ctrl
Cache Ctrl
Miss LRU
Bus Ctrl
Hit LRU
the
FSM
PREFETCH MODULE BLOCK DIAGRAM
Microchip
Tag Logic
PreFetch
Pre-Fetch
Hit Logic
Prefetch
Tag
web
PFM
site
Address
in
Encode
Cache
Line
CTRL
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1
• 16 fully associative lockable cache lines
• 16-byte cache lines
• Up to four cache lines allocated to data
• Two cache lines with address mask to hold
• Pseudo LRU replacement policy
• All cache lines are software writable
• 16-byte parallel memory fetch
• Predictive instruction prefetch
PIC32MX5XX/6XX/7XX
repeated instructions
Cache Line
Pre-Fetch
Features
PreFetch
Prefetch
RDATA
DS61156F-page 123