PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 75

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-11:
Legend:
Note
5220
5230
5240
5250
5260
5300
5310
5320
5330
5340
5350
5360
1:
I2C1STAT
I2C5MSK
I2C5BRG
I2C1CON
I2C1MSK
I2C1BRG
I2C5ADD
I2C5TRN
I2C5RCV
I2C1TRN
I2C1RCV
I2C3DD
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP
ACKSTAT
31/15
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
30/14
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLREL
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
A10M
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(CONTINUED)
GCSTAT
DISSLW
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD10
SMEN
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
IWCOL
GCEN
23/7
—
—
—
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
Baud Rate Generator Register
STREN
I2COV
22/6
—
—
—
—
—
—
—
—
—
—
—
—
ACKDT
21/5
D/A
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ADD<9:0>
MSK<9:0>
ACKEN
Transmit Register
Transmit Register
20/4
Receive Register
Receive Register
—
—
—
—
—
—
—
—
—
—
—
—
P
RCEN
19/3
—
—
—
—
—
—
—
—
—
—
—
—
S
Section 12.1.1 “CLR, SET and INV Registers”
18/2
PEN
R/W
—
—
—
—
—
—
—
—
—
—
—
—
RSEN
17/1
RBF
—
—
—
—
—
—
—
—
—
—
—
—
16/0
SEN
TBF
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000