PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 51

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
• Simple memory mapping with Fixed Mapping
• Cacheable (KSEG0) and non-cacheable (KSEG1)
© 2010 Microchip Technology Inc.
Note:
(KSEG0/KSEG1) mode address space
program space
runaway code
Translation (FMT) unit
address regions
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive
detailed information, refer to Section 3.
“Memory Organization” (DS61115) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
reference
source.For
4.1
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are illustrated in
4.1.1
Table 4-1
address
devices. Peripherals located on the PB bus are
mapped to 512-byte boundaries. Peripherals on the
FPB bus are mapped to 4-Kbyte boundaries.
PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX Memory
Layout
through
maps
PERIPHERAL REGISTERS
LOCATIONS
for
Table 4-44
the
Figure 4-1
PIC32MX5XX/6XX/7XX
contain the peripheral
through
DS61156F-page 51
Figure
4-6.