PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 92

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-24:
TABLE 4-25:
Legend:
Note
Legend:
Note
6000
6010
6020
6030
6040
6050
6060
6070
1:
1:
PORTA
PORTB
TRISA
ODCA
TRISB
ODCB
LATA
LATB
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
PORTB REGISTER MAP
TRISA15
ODCA15
TRISB15
ODCB15
LATA15
LATB15
31/15
RA15
31/15
RB15
—
—
—
—
—
—
—
—
TRISA14
ODCA14
TRISB14
ODCB14
LATA14
LATB14
30/14
RA14
30/14
RB14
—
—
—
—
—
—
—
—
TRISB13
ODCB13
LATB13
29/13
29/13
RB13
—
—
—
—
—
—
—
—
—
—
—
—
TRISB12
ODCB12
LATB12
(1)
28/12
28/12
RB12
—
—
—
—
—
—
—
—
—
—
—
—
TRISB11
ODCB11
LATB11
27/11
27/11
RB11
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10
ODCA10
TRISB10
ODCB10
LATA10
LATB10
26/10
RA10
26/10
RB10
—
—
—
—
—
—
—
—
TRISA9
ODCA9
TRISB9
ODCB9
LATA9
LATB9
25/9
RA9
25/9
RB9
—
—
—
—
—
—
—
—
TRISB8
ODCB8
LATB8
24/8
24/8
RB8
—
—
—
—
—
—
—
—
—
—
—
—
Bits
Bits
TRISA7
ODCA7
TRISB7
ODCB7
LATA7
LATB7
23/7
RA7
23/7
RB7
—
—
—
—
—
—
—
—
TRISA6
ODCA6
TRISB6
ODCB6
LATA6
LATB6
22/6
RA6
22/6
RB6
—
—
—
—
—
—
—
—
TRISA5
ODCA5
TRISB5
ODCB5
LATA5
LATB5
21/5
RA5
21/5
RB5
—
—
—
—
—
—
—
—
TRISA4
ODCA4
TRISB4
ODCB4
LATA4
LATB4
20/4
RA4
20/4
RB4
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISA3
ODCA3
TRISB3
ODCB3
LATA3
LATB3
19/3
RA3
19/3
RB3
—
—
—
—
—
—
—
—
(1)
TRISA2
ODCA2
TRISB2
ODCB2
LATA2
LATB2
18/2
RA2
18/2
RB2
—
—
—
—
—
—
—
—
TRISA1
ODCA1
TRISB1
ODCB1
LATA1
LATB1
17/1
RA1
17/1
RB1
—
—
—
—
—
—
—
—
TRISA0
ODCA0
TRISB0
ODCB0
LATA0
LATB0
16/0
RA0
16/0
RB0
—
—
—
—
for more
—
—
—
—
for more
0000
C6FF
0000
xxxx
0000
xxxx
0000
0000
0000
FFFF
0000
xxxx
0000
xxxx
0000
0000