PIC32MX575F512LT-80I/BG Microchip Technology, PIC32MX575F512LT-80I/BG Datasheet - Page 166

• Manufacturer Part Number: PIC32MX575F512LT-80I/BG
• Description: 512KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC32MX5XX/6XX/7XX
REGISTER 28-3:
DS61156F-page 166
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31-19
bit 18-16
bit 15
bit 14-11
bit 10-8
bit 7
UPLLEN
R/P
r-1
r-1
r-1
—
—
—
Reserved: Write ‘ 1 ’
FPLLODIV<2:0>: Default Postscaler for PLL bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
UPLLEN: USB PLL Enable bit
1 = Disable and bypass USB PLL
0 = Enable USB PLL
Reserved: Write ‘ 1 ’
UPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
Reserved: Write ‘ 1 ’
R/P-1
r-1
r-1
r-1
—
—
—
DEVCFG2: DEVICE CONFIGURATION WORD 2
FPLLMUL<2:0>
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
R/P
r-1
r-1
r-1
—
—
—
R/P-1
r-1
r-1
r-1
—
—
—
P = Programmable bit
r-1
r-1
r-1
r-1
—
—
—
—
R/P
R/P
R/P
r-1
—
© 2010 Microchip Technology Inc.
FPLLODIV<2:0>
UPLLIDIV<2:0>
FPLLIDIV<2:0>
r = Reserved bit
R/P
R/P
R/P
r-1
—
R/P
R/P
R/P
r-1
—
bit 24
bit 16
bit 8
bit 0