FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 170

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Functional Description
5.15.3.3
5.15.4
5.15.5
170
The data transfer phase continues the burst transfers with the data transmitter (ICH4 - writes, IDE
device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on
each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE
high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by
deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH4 pauses a
burst transaction to prevent an internal line buffer over or under flow condition, resuming once the
condition has cleared. It may also pause a transaction if the current PRD byte count has expired,
resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst termination
consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH4 can stop a burst
by asserting STOP, with the IDE device acknowledging by deasserting DMARQ. The IDE device
stops a burst by deasserting DMARQ and the ICH4 acknowledges by asserting STOP. The
transmitter then drives the STROBE signal to a high level. The ICH4 then drives the CRC value
onto the DD lines and deasserts DMACK#. The IDE device latches the CRC value on the rising
edge of DMACK#. The ICH4 terminates a burst transfer if it needs to service the opposite IDE
channel, if a Programmed I/O (PIO) cycle is executed to the IDE channel currently running the
burst, or upon transferring the last data from the final PRD.
CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The
CRC value is calculated for all data by both the ICH4 and the IDE device over the duration of the
Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid
STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst
segment, the ICH4 drives the CRC value onto the DD[15:0] signals. It is then latched by the IDE
device on deassertion of DDACK#. The IDE device compares the ICH4 CRC value to its own and
reports an error if there is a mismatch.
Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the ICH4 supports the Ultra ATA/66 protocol. The Ultra ATA/66
protocol is enabled via configuration bits 3:0 at offset 54h. The two protocols are similar, and are
intended to be device driver compatible. The Ultra ATA/66 logic can achieve transfer rates of up to
66 MB/s.
To achieve the higher data rate, the timings are shortened and the quality of the cable is improved
to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and
will still plug into the standard IDE connector. The Ultra ATA/66 protocol also supports a 44 MB/s
mode.
Ultra ATA/100 Protocol
When the ATA_FAST bit is set for any of the four IDE devices, then the timings for the transfers to
and from the corresponding device run at a higher rate. The ICH4 Ultra ATA/100 logic can achieve
read transfer rates up to 100MB/s, and write transfer rates up to 88.9MB/s.
The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further
cable improvements are required when implementing Ultra ATA/100.
Intel
®
82801DB ICH4 Datasheet