FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 571

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table A-2. Intel
Intel
Channel 0 DMA Base & Current
Address Register
Channel 0 DMA Base & Current
Count Register
Channel 0 DMA Memory Low Page
Register
Channel 0–3 DMA Command
Register
Channel 0–3 DMA Status Register
Channel 0–3 DMA Write Single
Mask Register
Channel 0–3 DMA Channel Mode
Register
Channel 0–3 DMA Clear Byte
Pointer Register
Channel 0–3 DMA Master Clear
Register
Channel 0–3 DMA Clear Mask
Register
Channel 0–3 DMA Write All Mask
Register
Timer Control Word Register
Timer Control Word Register Read
Back
Counter Latch Command
Interval Timer Status Byte Format
Counter Access Port Register
Initialzation Command Word 1
Register
Initialzation Command Word 2
Register
Master Controller Initialzation
Command Word 3 Register
Slave Controller Initialzation
Command Word 3 Register
Initialzation Command Word 4
Register
Operational Control Word 1
Registerr
Operational Control Word 2
Registerr
®
82801DB ICH4 Datasheet
Register Name
®
ICH4 Fixed I/O Registers (Sheet 1 of 2)
Port
0Ah
0Bh
0Ch
0Dh
0Eh
A1h
00h
01h
87h
08h
08h
0Fh
43h
40h
40h
20h
21h
21h
21h
21h
20h
8254 Interrupt Controller
Timer I/O Registers
Section 9.2.1, “DMABASE_CA—DMA Base and Current Address
Registers” on page 9-316
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count Registers”
on page 9-316
Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page Registers” on
page 9-317
Section 9.2.4, “DMACMD—DMA Command Register” on page 9-317
Section 9.2.5, “DMASTA—DMA Status Register” on page 9-318
Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask Register” on
page 9-318
Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register” on
page 9-319
Section 9.2.8, “DMA Clear Byte Pointer Register” on page 9-319
Section 9.2.9, “DMA Master Clear Register” on page 9-320
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register” on
page 9-320
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register” on
page 9-320
Section 9.3.1, “TCW—Timer Control Word Register” on page 9-321
Section 9.3.1.1, “RDBK_CMD—Read Back Command” on page 9-322
Section 9.3.1.2, “LTCH_CMD—Counter Latch Command” on page 9-322
Section 9.3.2, “SBYTE_FMT—Interval Timer Status Byte Format Register”
on page 9-323
Section 9.3.3, “Counter Access Ports Register” on page 9-323
Section 9.4.1, “ICW1—Initialization Command Word 1 Register” on
page 9-325
Section 9.4.2, “ICW2—Initialization Command Word 2 Register” on
page 9-326
Section 9.4.3, “ICW3—Master Controller Initialization Command Word 3
Register” on page 9-326
Section 9.4.4, “ICW3—Slave Controller Initialization Command Word 3
Register” on page 9-327
Section 9.4.5, “ICW4—Initialization Command Word 4 Register” on
page 9-327
Section 9.4.6, “OCW1—Operational Control Word 1 (Interrupt Mask)
Register” on page 9-327
Section 9.4.7, “OCW2—Operational Control Word 2 Register” on
page 9-328
DMA I/O Registers
Datasheet Location
Register Index
571