FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 88

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FW82801DB S L66K

Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DB S L66K

Lead Free Status / RoHS Status
Supplier Unconfirmed
Functional Description
5.3.1.3
5.3.1.4
5.3.1.5
88
Table 5-4. Cycle Type Bit Definitions
Table 5-5. Transfer Size Bit Definition
Table 5-6. SYNC Bit Definition
Cycle Type / Direction (CYCTYPE + DIR)
The ICH4 will always drive bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0.
Size
Bits[3:2] are reserved. The ICH4 always drives them to 00. Peripherals running bus master cycles
are also supposed to drive 00 for bits 3:2, however, the ICH4 will ignore those bits. Bits[1:0] are
encoded as shown in
SYNC
Valid values for the SYNC field are provided in
NOTE: All other combinations are RESERVED.
Bits[3:2]
Bits[1:0]
Bits[3:0]
00
00
01
01
10
10
11
0000
0101
0110
1001
1010
00
01
10
11
Bit[1]
Table 5-4
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
master cycle drives this combination, the ICH4 may abort the transfer.
32-bit transfer (4 bytes)
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request
deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the Intel
this encoding. It will instead use the Long Wait encoding (see next encoding below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding
driven by the ICH4 for bus master cycles, rather than the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and
more DMA transfers desired to continue after this transfer. This value is valid only on DMA
transfers and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#
signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious
error in this transfer. For DMA transfers, this not only indicates an error, but also indicates
DMA request deassertion and no more transfers desired for that channel.
0
1
0
1
0
1
x
Table
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this value, the
Intel
shows the valid bit encodings:
®
5-5.
ICH4 will abort the cycle.
®
ICH4 will never drive this combination. If a peripheral running a bus
Table
Indication
5-6.
Size
Definition
Intel
®
82801DB ICH4 Datasheet
®
ICH4 will not use

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