FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 48

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Signal Description
2.12
2.13
48
Table 2-11. Processor Interface Signals (Sheet 2 of 2)
Table 2-12. SM Bus Interface Signals
Table 2-13. System Management Interface Signals
SMBus Interface
System Management Interface
SMBALERT#/
CPUPWRGD
SMLINK[1:0]
INTRUDER#
SMBDATA
A20GATE
SMBCLK
GPIO[11]
RCIN#
Name
Name
Name
Type
Type
Type
I/OD
I/OD
I/OD
OD
I
I
I
I
Keyboard Controller Reset CPU: The keyboard controller can generate INIT#
to the processor. This saves the external OR gate with the ICH4’s other
sources of INIT#. When the ICH4 detects the assertion of this signal, INIT# is
generated for 16 PCI clocks.
NOTE: The ICH4 ignores RCIN# assertion during transitions to the S3, S4
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
alternative method to force the A20M# signal active. It saves the external OR
gate needed with various other PCIsets.
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input. This is an open-drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH4’s PWROK and
VRMPWRGD signals.
SMBus Data: External pull-up is required.
SMBus Clock: External pull-up is required.
SMBus Alert: This signal is used to wake the system or generate SMI#. If not
used for SMBALERT#, it can be used as a GPI.
Intruder Detect: This signal can be set to disable the system if the box is
detected open. This signal’s status is readable, so it can be used like a GPI if
the Intruder Detection is not needed.
System Management Link: SMBus link to optional external system
management ASIC or LAN controller. External pull-ups are required. Note that
SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]
corresponds to an SMBus Data signal.
and S5 states.
Description
Description
Description
Intel
®
82801DB ICH4 Datasheet