FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 452

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

SMBus Controller Registers (D31:F3)
13.1.3
13.1.4
452
CMD—Command Register (SMBUS—D31:F3)
Address:
Default Value:
STA—Device Status Register (SMBUS—D31:F3)
Address:
Default Value:
15:10
10:9
Bit
4:0
15
14
13
12
11
Bit
8
7
6
5
9
8
7
6
5
4
3
2
1
0
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — RO. Reserved as 0.
Received Target Abort (RTA) — RO. Reserved as 0.
Signaled Target Abort (STA) — R/WC.
Set when the function is targeted with a transaction that the ICH4 terminates with a target abort.
Software resets STA to 0 by writing a 1 to this bit location.
DEVSEL# Timing Status (DEV_STS) — RO . This 2-bit field defines the timing for DEVSEL#
assertion for positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Reserved
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — RO. Reserved as 0.
Memory Space Enable (MSE) — RO. Reserved as 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
04–05h
0000h
06–07h
0280h
Description
Description
Attributes:
Size:
Attributes:
Size:
Intel
RO R/W
16 bits
RO R/WC
16 bits
®
82801DB ICH4 Datasheet