FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 432

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

EHCI Controller Registers (D29:F7)
12.2
12.2.1
12.2.1.1
432
Table 12-2. Enhanced Host Controller Capability Registers
Note: When the USB EHCI function is in the D3 PCI power state, accesses to the USB EHCI memory
Memory-Mapped I/O Registers
The USB 2.0 EHCI memory-mapped I/O space is composed of two sets of registers: Capability
Registers and Operational Registers.
range are ignored and result in a master abort. Similarly, if the Memory Space Enable (MSE) bit is
not set in the Command register in configuration space, the memory range will not be decoded by
the ICH4 Enhanced Host Controller (EHC). If the MSE bit is not set, the ICH4 must default to
allowing any memory accesses for the range specified in the BAR to go to PCI. This is because the
range may not be valid and, therefore, the cycle must be made available to any other targets that
may be currently using that range.
Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the Host Controller Capability Registers, only the Structural Parameters
register is writable. This register is implemented in the Suspend well and is only reset by the
standard suspend-well hardware reset, not by HCRESET or the D3-to-D0 reset.
NOTE: “Read/Write-Special” means that the register is normally read-only, but may be written when the
CAPLENGTH—Capability Registers Length Register
Offset:
Default Value:
08–0Bh
02–03h
04–07h
Offset
Bit
7:0
00h
WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during
initialization, their contents must not get modified by HCRESET or D3-to-D0 internal reset.
Capability Register Length Value — RO. This register is used as an offset to add to the Memory
Base Register to find the beginning of the Operational Register Space. This is fixed at 20h,
indicating that the Operation Registers begin at offset 20h.
HCIVERSION
HCSPARAMS
HCCPARAMS
CAPLENGTH
Mnemonic
00h
20h
Capabilities Registers Length
Host Controller Interface Version Number
Host Controller Structural Parameters
Host Controller Capability Parameters
Register Name
Description
Attribute:
Size:
RO
8 bits
Intel
®
82801DB ICH4 Datasheet
00103206h
00006871h
Default
0100h
20h
R/W-Special
Type
RO
RO
RO