FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 538

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Electrical Characteristics
538
Table 17-20. Power Management Timings
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. This transition is clocked off the 66 MHz CLK66. 1 CLK66 is approximately 15 ns.
3. The ICH4 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
5. The ICH4 has no maximum timing requirement for this transition. It is up to the system designer to determine
t183a SLPS5# inactive to SLP_S4# inactive
t183b SLPS4# inactive to SLP_S3# inactive
t194a SLP_S3# active to SLP_S4# active
t198a Wake Event to SLP_S4# inactive (S4 Wake)
t198b Wake Event to SLP_S3# inactive (S3 Wake)
t198d SLP_S5# inactive to SLP_S4# inactive
t198e SLP_S4# inactive to SLP_S3# inactive
Sym
t181
t182
t183
t184
t185
t186
t187
t188
t189
t190
t192
t193
t194
t195
t196
t197
t198
t204
t205
t206
t220
for this cycle getting to the ICH4 is dependant on the processor and the memory controller.
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
VccSus active to SLP_S5#, SUS_STAT# and
PCIRST# active
RSMRST# inactive to SUSCLK running, SLP_S5#
inactive
Vcc active to STPCLK# and CPUSLP# inactive, and
processor Frequency Strap signals high
PWROK and VRMPWRGD active and
SYS_RESET# inactive to SUS_STAT# inactive and
processor Frequency Straps latched to Strap Values
Processor Reset Complete to Frequency Strap
signals unlatched from Strap Values
STPCLK# active to Stop Grant cycle
Stop Grant cycle to CPUSLP# active
S1 Wake Event to CPUSLP# inactive
CPUSLP# inactive to STPCLK# inactive
CPUSLP# active to SUS_STAT# active
SUS_STAT# active to PCIRST# active
PCIRST# active to SLP_S3# active
SLP_S4# active to SLP_S5# active
SLP_S3# active to PWROK, VRMPWRGD inactive
PWROK, VRMPWRGD inactive to Vcc supplies
inactive
Wake Event to SLP_S5# inactive
CPU I/F signals latched prior to STPCLK# active
Break Event to STPCLK# inactive
STPCLK# inactive to processor I/F signals unlatched
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
Parameter
3.87
Min
N/A
240
32
60
20
30
1
1
7
1
2
9
1
1
1
0
1
1
1
1
1
0
3120
1880
Max
N/A
245
110
50
50
38
63
25
21
10
10
10
2
2
9
4
2
2
2
2
2
4
2
Intel
®
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
PCI CLK
PCICLK
PCICLK
CLK66
CLK66
82801DB ICH4 Datasheet
Units
ms
ms
ns
ns
µs
ns
ns
ns
Notes
1, 6
7
1
2
3
4
4
1
1
1
1
5
1
1
1
1
1
2
17-20
17-20
17-20
17-20
17-20
17-20
17-20
17-21
17-20
17-21
17-20
17-20
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-21
17-22
17-22
17-22
Fig