FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 405

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.1.16
Intel
®
82801DB ICH4 Datasheet
USB_LEGKEY—USB Legacy Keyboard/Mouse Control
Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
This register is implemented separately in each of the USB UHCI functions. However, the enable
and status bits for the trapping logic are OR’d and shared, respectively, since their functionality is
not specific to any one host controller.
Bit
15
14
13
12
11
10
9
8
SMI Caused by End of Pass-through (SMIBYENDPS) — R/WC. Indicates if the event occurred.
Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up
to the SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred
Reserved
PCI Interrupt Enable (USBPIRQEN) — R/W. Used to prevent the USB controller from generating an
interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to
generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software.
0 = Disable
1 = Enable
SMI Caused by USB Interrupt (SMIBYUSB) — RO. Indicates if an interrupt event occurred from this
controller. The interrupt from the controller is taken before the enable in bit 13 has any effect to create
this read-only bit. Note that even if the corresponding enable bit is not set in the Bit 4, then this bit may
still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit will have no
1 = Event Occurred.
SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate
Pass-Through Logic allows specific port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Write (TRAPBY60W) — R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate
Pass-Through Logic allows specific port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
effect.
C0
2000h
–
C1h
Description
Attribute:
Size:
USB UHCI Controllers Registers
R/W, R/WC, RO
16 bits
405