FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 249

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.4
Intel
®
Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
82801DB ICH4 Datasheet
Memory Map
Table 6-4
Cycles that arrive from the hub interface that are not directed to any of the internal memory targets
that decode directly from hub interface will be driven out on PCI. The ICH4 may then claim the
cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is
enabled, the cycle can be forwarded to LPC.
PCI cycles generated by an external PCI master will be positively decoded unless it falls in the
PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If the
cycle is not in the I/O APIC or LPC ranges, it will be forwarded up the hub interface to the Host
controller. PCI masters can not access the memory ranges for functions that decode directly from
Hub Interface.
FFC0 0000–FFC7 FFFFh
FFC8 0000–FFCF FFFFh
FFD0 0000–FFD7 FFFFh
FFD8 0000–FFDF FFFFh
FFE8 0000–FFEF FFFFh
FFB8 0000–FFBF FFFFh
FEC0 0000–FEC0 0100h
FFA0 0000–FFA7 FFFFh
FFA8 0000–FFAF FFFFh
FFF0 0000–FFF7 FFFFh
FFB0 0000–FFB7 FFFFh
FFF8 0000–FFFF FFFFh
FF80 0000–FF87 FFFFh
FF88 0000–FF8F FFFFh
FF90 0000–FF97 FFFFh
FF98 0000–FF9F FFFFh
FF70 0000–FF7F FFFFh
FF30 0000–FF3F FFFFh
FF60 0000–FF6F FFFFh
FF20 0000–FF2F FFFFh
FF50 0000–FF5F FFFFh
FF10 0000–FF1F FFFFh
FF40 0000–FF4F FFFFh
FF00 0000–FF0F FFFFh
0000 0000–000D FFFFh
000E 0000–000F FFFFh
FFE0 000–FFE7 FFFFh
4 KB anywhere in 4 GB
0010 0000h–TOM
Memory Range
(Top of Memory)
shows (from the processor perspective) the memory ranges that the ICH4 will decode.
range
I/O APIC inside
Integrated LAN
Main Memory
Controller
Target
FWH
ICH4
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
TOM registers in Host controller
Bit 7 in FWH Decode Enable Register is set
Bit 0 in FWH Decode Enable Register
Bit 1 in FWH Decode Enable Register
Bit 2 in FWH Decode Enable Register is set
Bit 3 in FWH Decode Enable Register is set
Bit 4 in FWH Decode Enable Register is set
Bit 5 in FWH Decode Enable Register is set
Bit 6 in FWH Decode Enable Register is set.
Always enabled.
The top two 64 KB blocks of this range can be swapped, as
described in
Bit 3 in FWH Decode Enable 2 Register is set
Bit 2 in FWH Decode Enable 2 Register is set
Bit 1 in FWH Decode Enable 2 Register is set
Bit 0 in FWH Decode Enable 2 Register is set
Enable via BAR in Device 29:Function 0 (Integrated LAN
Controller)
Section
Dependency/Comments
7.4.1.
Register and Memory Mapping
249