FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 40

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FW82801DB S L66K

Manufacturer Part Number
FW82801DB S L66K
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DB S L66K

Lead Free Status / RoHS Status
Supplier Unconfirmed
Signal Description
2.3
2.4
2.5
40
Table 2-3. EEPROM Interface Signals
Table 2-4. Firmware Hub Interface Signals
Table 2-5. PCI Interface Signals (Sheet 1 of 3)
EEPROM Interface
Firmware Hub Interface
PCI Interface
EE_SHCLK
C/BE[3:0]#
FWH[3:0] /
EE_DOUT
LFRAME#
AD[31:0]
FWH[4] /
LAD[3:0]
EE_DIN
EE_CS
Name
Name
Name
Type
Type
Type
I/O
I/O
I/O
I/O
O
O
O
I
EEPROM Shift Clock: This signal is the serial shift clock output to the
EEPROM.
EEPROM Data In: This signal transfers data from the EEPROM to the Intel
ICH4. This signal has an integrated pull-up resistor.
EEPROM Data Out: EE_DOUT transfers data from the ICH4 to the EEPROM.
EEPROM Chip Select: EE_CS is the chip select signal to the EEPROM.
Firmware Hub Signals: FWH[3:0] are muxed with LPC address signals.
Firmware Hub Signals: FWH[4] is muxed with the LPC LFRAME# signal.
PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical address (32 bits).
During subsequent clocks, AD[31:0] contain data. The Intel
on AD[31:0] during the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable signals
are multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# define the bus command. During the data phase, C/
BE[3:0]# define the Byte Enables.
All command encodings not shown are reserved. The ICH4 does not decode
reserved values, and therefore will not respond if a PCI master generates a
cycle using one of the reserved values.
C/BE[3:0]#
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 1 0
0 1 1 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 1 0
1 1 1 1
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
Description
Description
Description
Intel
®
82801DB ICH4 Datasheet
®
ICH4drives all 0s
®

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