FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 366

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

LPC Interface Bridge Registers (D31:F0)
366
1:0
Bit
12
10
11
9
8
7
6
5
4
3
2
Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
1 = Set under any of the following conditions:
Microcontroller SMI# Status (MCSMI_STS) — R/WC.
0 = Indicates that there has been no access to the power management microcontroller range (62h or
1 = Set if there has been an access to the power management microcontroller range (62h or 66h). If
GPE0_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also
set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit
set in the ALT_GP_SMI_EN register. Bits that are not routed to cause an SMI# will have no effect on
this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0_STS — RO. This bit is a logical OR of the bits in the GPE0_STS register that also have the
corresponding bit set in the GPE0_EN register.
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset
PMBASE+00h) that can cause an SMI#.
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
Reserved
SWSMI_TMR_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Set by the hardware when the Software SMI# Timer expires.
APM_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = SMI# was generated by a write access to the APM control register with the APMC_EN bit set.
SLP_SMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy
Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be
active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
BIOS_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = SMI# was generated due to ACPI software requesting attention (writing a 1 to the GBL_RLS bit
Reserved
66h). This bit is cleared by software writing a 1 to the bit position.
this bit is set and the MCSMI_EN bit is also set, the ICH4 will generate an SMI#.
with the BIOS_EN bit set).
•
•
Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN
bits are also set.
Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are also
set.
Description
Intel
®
82801DB ICH4 Datasheet