FW82801DB S L66K Intel, FW82801DB S L66K Datasheet - Page 224

• Manufacturer Part Number: FW82801DB S L66K
• Manufacturer: Intel

Specifications of FW82801DB S L66K

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Functional Description
.
5.18.7.2
224
Table 5-95. Command Types
Format of Read Command
The external master performs Byte Read commands to the ICH4 SMBus Slave interface. The
“Command” field (bits 11–18) indicate which register is being accessed. The Data field (bits 30-
37) contain the value that should be read from that register.
format.
Command
9–FFh
Type
0
1
2
3
4
5
6
7
8
Table 5-97
Reserved
Reserved
WAKE/SMI#: Wake system if it is not already awake. If system is already awake, then an
SMI# will be generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already
Unconditional Powerdown: This command sets the PWRBTNOR_STS bit, and has the
same effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: The will cause a hard reset of the system (does not
include cycling of the power supply). This is equivalent to a write to the CF9h register with
bits 2:1 set to 1, but bit 3 set to 0.
HARD RESET SYSTEM: The will cause a hard reset of the system (including cycling of the
power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
Disable the TCO Messages: This command will disable the Intel
Heartbeat and Event messages (as described in
been executed, Heartbeat and Event message reporting can only be re-enabled by
assertion and deassertion of the RSMRST# signal.
WD RELOAD: Reload watchdog timer.
Reserved
SMLINK_SLV_SMI: When ICH4 detects this command type while in the S0 state, it sets the
SMLINK_SLV_SMI_STS bit (see
system is in an S0 state. If the message is received during S1–S5 states, the ICH4
acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set.
NOTE: It is possible that the system transitions out of the S0 state at the same time that the
shows the register mapping for the data byte.
awake. The SMI handler should then clear this bit.
SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS
bit may get set but not serviced before the system goes to sleep. Once the system
returns to S0, the SMI associated with this bit would then be generated. Software
must be able to handle this scenario.
Section
Description
9.9.7). This command should only be used if the
Table 5-96
Section
Intel
5.13.2). Once this command has
shows the Read Cycle
®
82801DB ICH4 Datasheet
®
ICH4 from sending