LMK03200ISQE/NOPB National Semiconductor, LMK03200ISQE/NOPB Datasheet
LMK03200ISQE/NOPB
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LMK03200ISQE/NOPB Summary of contents
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... Medical ■ Test and Measurement ■ Military / Aerospace System Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation LMK03200 Family Features ■ Integrated VCO with very low phase noise floor ■ Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz ■ ...
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Functional Block Diagram www.national.com 2 30088701 ...
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General Description .............................................................................................................................. 1 Target Applications ............................................................................................................................... 1 Features .............................................................................................................................................. 1 System Diagram ................................................................................................................................... 1 Functional Block Diagram ...................................................................................................................... 2 Connection Diagram ............................................................................................................................. 5 Pin Descriptions .................................................................................................................................. 6 Absolute Maximum Ratings .................................................................................................................... 7 Recommended Operating Conditions ..................................................................................................... 7 Package Thermal ...
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PLL_N [17:0] -- PLL N Divider ...................................................................................... 28 2.10.2 VCO_DIV [3:0] -- VCO Divider ...................................................................................... 29 2.10.3 PLL_CP_GAIN [1:0] -- PLL Charge Pump Gain .............................................................. 29 2.10.4 PLL_N_DLY [3:0] - Global Skew Adjust, Lead ................................................................. 30 3.0 Application Information ...
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Connection Diagram 48-Pin LLP Package 5 30088702 www.national.com ...
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Pin Descriptions Pin # 13, 16, 19, 22, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10, 26, 30, 31, 33, 37, 40, 43 14, ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Recommended Operating Conditions Parameter Ambient Temperature Power Supply Voltage Note 1: " ...
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Electrical Characteristics ≤ ≤ ≤ (3.15 V Vcc 3.45 V, -40 ° most likely parametric norms at Vcc = 3 characterization and are not guaranteed). Symbol Parameter Power Supply Current I CC (Note ...
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Symbol Parameter PLL 1/f Noise at 10 kHz Offset PN10kHz Normalized to 1 GHz Output Frequency Normalized Phase Noise Contribution PN1Hz (Note 8) f VCO Tuning Range Fout Allowable Temperature Drift for |Δ Continuous Lock Output Power to ...
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Symbol Parameter Clock Distribution Section - LVDS Clock Outputs Jitter Additive RMS Jitter (Note 12) ADD V Differential Output Voltage OD Change in magnitude of V ΔV OD complementary output states V Output Offset Voltage OS Change in magnitude of ...
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Symbol Parameter t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t Clock Pulse Width Low CWL t Clock to Enable Set Up Time ES t Enable to ...
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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current Charge Pump Sink Current Charge Pump Sink Current Charge Pump Source Current Charge ...
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Typical Performance Characteristics LVDS Vod LVDS Output Buffer Noise Floor (Notes 17, 18) Delay Noise Floor Note 16: These plots show performance at frequencies beyond what the part is guaranteed to operate at to give the user an idea of ...
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Functional Description The LMK03200 family of precision clock conditioners com- bine the functions of jitter cleaning/reconditioning, multiplica- tion, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high per- formance Integer-N Phase ...
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GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. SYNC* is not used in VCO bypass mode. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic ...
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DIGITAL LOCK DETECT The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector generated delay of ε. To indicate a locked state the phase error must be ...
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GLOBAL DELAYS After the N divider and R divider are two delays PLL_N_DLY and PLL_R_DLY. They support a 150 ps step size and range from 0 to 2250 ps of total delay. When using the 0-delay mode, these delays ...
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General Programming Information The LMK03200 family of devices are programmed using sev- eral 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR [3:0] form ...
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PLL_MUX value to indicate the device is phase locked. 0_DELAY_MODE = 1 reverts the LD pin back to digital lock detect. The device is now phase locked and synchronized with the reference clock. ...
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Begin monitoring LD pin for frequency calibration routine complete signal. The device now begins the frequency calibration routine, when it completes the LD pin will go high since PLL_MUX was programmed with the active high option for the frequency ...
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The device now beings the frequency calibration routine, when it completes the LD pin will go high since PLL_MUX was programmed with the active high option for lock detect and DLD_MODE2 = 1. When the LD pin goes high, or ...
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CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN 0_DELAY_ MODE DLD_MODE2 RESET Register www.national.com 22 ...
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DIV4 Vboost POWERDOWN EN_CLKout_Global Register EN_Fout 23 www.national.com ...
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Register Registers R0 through R7 control the eight clock outputs. Reg- ister R0 controls CLKout0, Register R1 controls CLKout1, and so on. There are some additional bit in register R0 called RE- SET, DLD_MODE2, 0_DELAY_MODE, and ...
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Activate 0-Delay Mode This bit is only in register R0 and is used for activating the 0- delay mode. Once the frequency calibration routine is com- plete - as determined by monitoring the LD output in ...
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CLKoutX_DIV [7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX bit must be set to either "Divided" or "Divided and Delayed" mode. After all ...
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Register R11 This register only has one bit and only needs to be pro- grammed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Other- wise automatically ...
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PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes. Note that PLL_MUX = 3 and PLL_MUX = 4 have alternate functionality if DLD_MODE2 (section ...
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PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value also influenced by the VCO Di- Total vider value ...
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PLL_N_DLY [3:0] - Global Skew Adjust, Lead These bits control the delay stage in front of the N input of the phase detector. The affect of adjusting this delay is to lead the phase of the clock outputs uniformly ...
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Application Information 3.1 SYSTEM LEVEL DIAGRAM Figure 6 shows an LMK03200 family device used in a typical application. In this setup the clock may be multiplied, recon- ditioned, and redistributed. Both the OSCin/OSCin* and CLK- outX/CLKoutX* pins can be ...
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LOOP FILTER The internal charge pump is directly connected to the inte- grated loop filter components. The first and second pole of the loop filter are externally attached as shown in the loop filter is designed, it must be ...
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CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following ta- ble serves to provide enough information to allow the user to Table 3.5 - Block Current Consumption Block Condition Entire device, All outputs ...
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THERMAL MANAGEMENT Power consumption of the LMK03200 family of devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, ...
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FIGURE 9. Differential LVPECL Operation, DC Coupling FIGURE 10. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 3.7.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. ...
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Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal possible to use an LVPECL driver as one or two separate ...
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FIGURE 17. Differential Sine Wave Input FIGURE 18. Recommended OSCin Power for Operation with a Sine Wave Input 3.9 MORE THAN EIGHT OUTPUTS WITH AN LMK03200 FAMILY DEVICE The LMK03200 family devices include eight outputs. When more than 8 outputs ...
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DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY The differential voltage of a differential signal can be de- scribed by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a ...
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Physical Dimensions inches (millimeters) unless otherwise noted Ordering Information Order Number VCO Version LMK03200ISQX 1.24 GHz LMK03200ISQ 1.24 GHz LMK03200ISQE 1.24 GHz Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Performance Grade Packing 800 fs 2500 Unit Tape ...
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