LMK03200ISQE/NOPB National Semiconductor, LMK03200ISQE/NOPB Datasheet - Page 18

• Manufacturer Part Number: LMK03200ISQE/NOPB
• Description: IC CLOCK CONDITIONER PREC 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK03200ISQE/NOPB

• Pll: Yes
• Input: Clock
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:9
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.296GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.296GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK03200ISQETR

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2.0 General Programming
Information
The LMK03200 family of devices are programmed using sev-
eral 32-bit registers which control the device's operation. The
registers consist of a data field and an address field. The last
4 register bits, ADDR [3:0] form the address field. The re-
maining 28 bits form the data field DATA [27:0].
During programming, LEuWire is low and serial data is
clocked in on the rising edge of CLKuWire (MSB first). When
LE goes high, data is transferred to the register bank selected
by the address field. Only registers R0 to R8, R11, and R13
to R15 need to be programmed for proper device operation.
For the frequency calibration routine to work properly OSCin
must be driven by a valid signal when R15 is programmed.
Any changes to the PLL_R divider or OSCin require R15 to
be programmed again while 0_DELAY_MODE = 0 to activate
the frequency calibration routine.
2.1 Recommended Programming Sequence, without 0-
Delay Mode
The recommended programming sequence involves pro-
gramming R0 with the reset bit set (RESET = 1) to ensure the
device is in a default state. It is not necessary to program R0
again, but if R0 is programmed again, the reset bit is pro-
grammed clear (RESET = 0). Registers are programmed in
order with R15 being the last register programmed. An ex-
ample programming sequence is shown below.
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2.2 Recommended Programing Sequence, with 0-Delay
Mode
The lock procedure when using the 0-delay mode has two
steps. The first is to complete the frequency calibration routine
for the target frequency while not in 0-delay mode. The sec-
ond step is to activate 0-delay mode and re-program the
PLL_N divider to accommodate the additional divide in the
clock output path so that phase lock can be achieved with the
reference input clock.
Global_CLK_EN and each output being used should be en-
abled in step 1. If the user desires for no output from the clock
outputs during frequency lock, the GOE pin should be held
low.
Step 1
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Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bit
is set in R0, the other R0 bits are ignored.
— If R0 is programmed again, the reset bit is programmed
Program R0 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
Program R8 for optimum phase noise performance.
Program R9 with Vboost setting if necessary.
Program R11 with DIV4 setting if necessary.
Program R13 with oscillator input frequency and internal
loop filter values.
Program R14 with Fout enable bit, global clock output bit,
power down setting, PLL mux setting, and PLL_R divider.
Program R15 with PLL charge pump gain, VCO divider,
and PLL N divider. The frequency calibration routine
starts.
GOE pin is held low to keep outputs from toggling.
Disabling the clock output with MICROWIRE should not
be used so that when more than one clock output is used,
they will all be synchronized together when using
clear (RESET = 0).
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Now the LD pin should be monitored for the frequency cali-
bration routine completed signal to be asserted if PLL_MUX
was set to 3 or 4 and DLD_MODE2 = 1. Otherwise wait 2 ms
for the frequency calibration routine to complete. Once the
frequency calibration routine is completed step 2 may be ex-
ecuted to achieve 0-delay mode. With the addition of the clock
output divide in the feedback path, the total N feedback divide
will change and the device will need to be programmed in this
step to accommodate this extra divide.
Step 2
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The device will now synchronize clock outputs with reference
input. As soon as the device is settled the LD pin will be as-
0_DELAY_MODE. Otherwise a separate SYNC* is
required ensure all outputs are synchronized together
after all steps are completed.
Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bit
is set in R0, the other R0 bits are ignored.
— If R0 is programmed again, the reset bit is programmed
Program R0 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
Outputs being used should be enabled.
— R0: DLD_MODE2 = 1 (Digital Lock Detect is now
— R0: 0_DELAY_MODE = 0
— R0: FB_MUX = desired feedback path for 0-delay
— RX: CLKoutX_EN = 1 for used clock outputs.
Program R8 for optimum phase noise performance.
Program R9 with Vboost setting if necessary.
Program R11 with DIV4 setting if necessary.
Program R13 with oscillator input frequency and internal
loop filter values.
Program R14 with Fout enable bit, global clock output bit,
power down setting, PLL mux setting, PLL_R divider, and
global PLL R delay.
— R14: EN_CLKout_Global = 1
— R14: PLL_MUX = 3 or 4 for frequency calibration
Program R15 with PLL charge pump gain, VCO divider,
PLL N divider, and global PLL N delay. The frequency
calibration routine starts.
Program R0 with the same settings as in step 1 except:
— 0_DELAY_MODE = 1 to activate 0-delay mode.
The output being used for feedback must be enabled for
the device to lock. This means that...
— GOE pin is high. (set high if low from step 1).
— SYNC* pin is high.
— CLKoutX_EN bit is 1. (For all clocks being used)
— EN_CLKout_Global bit is 1.
Special feedback cases:
— When CLKout 5 is used for feedback, CLKout 6 must
— When FBCLKin/FBCLKin* is used for feedback,
Program R15 with new PLL_N value.
clear (RESET = 0).
Frequency Calibration Routine Complete)
mode.
routine complete signal.
also be enabled (CLKout6_EN = 1). The configuration
of the channel does not matter.
CLKout 5 and CLKout 6 must be enabled
(CLKout5_EN = 1 and CLKout6_EN = 1). The
configuration of the channels does not matter, except
when CLKout 5 or CLKout 6 is the source channel
which drives FBCLKin/FBCLKin*.