LMK03200ISQE/NOPB National Semiconductor, LMK03200ISQE/NOPB Datasheet - Page 28

• Manufacturer Part Number: LMK03200ISQE/NOPB
• Description: IC CLOCK CONDITIONER PREC 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK03200ISQE/NOPB

• Pll: Yes
• Input: Clock
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:9
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.296GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.296GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK03200ISQETR

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2.9.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below
lists several different modes. Note that PLL_MUX = 3 and
PLL_MUX = 4 have alternate functionality if DLD_MODE2
(section
2) is set.
Analog Lock Detect outputs the state of the charge pump on
the LD pin. While the charge pump is on, the LD pin is low.
While the charge pump is off, the LD pin is high. By using two
resistors, a capacitor, diode, and comparator a lock detect
circuit may be constructed
pump will only turn on momentarily once every period of the
phase detector frequency. "N Divider Output/2" and "R Di-
vider Output/2" output half the frequency of the phase detec-
tor on the LD pin. When the device is locked, these
frequencies should be the same. These options are useful for
debugging.
Note 19: If DLD_MODE2 is set, this functionality is redefined to "Frequency
Calibration Routine Complete (Active High)." See
Digital Lock Detect Mode 2
Note 20: If DLD_MODE2 is set, this functionality is redefined to "Frequency
Calibration Routine Complete (Active Low)." See
Digital Lock Detect Mode 2
Note 21: For more information on lock detect circuits, see chapter 32 of PLL
Performance, Simulation and Design Handbook, Fourth Edition by Dean
Banerjee.
PLL_MUX [3:0]
12 to 15
10
11
2.4.2 DLD_MODE2 bit -- Digital Lock Detect Mode
0
1
2
3
4
5
6
7
8
9
Output Type
Open Drain
Open Drain
for more information.
for more information.
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
NMOS
PMOS
Hi-Z
(Note
21). When in lock the charge
Invalid
Invalid
Invalid
Analog Lock Detect
Analog Lock Detect
Analog Lock Detect
Digital Lock Detect
Digital Lock Detect
N Divider Output/2
R Divider Output/2
2.4.2 DLD_MODE2 bit --
Disabled (default)
(50% Duty Cycle)
(50% Duty Cycle)
LD Pin Function
2.4.2 DLD_MODE2 bit --
(Active High)
(Active Low)
Logic High
Logic Low
(Note 19)
(Note 20)
28
2.9.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
2.9.4 EN_CLKout_Global bit -- Global Clock Output
Enable
This bit overrides the individual CLKoutX_EN bits. When this
bit is set to 0, all clock outputs are disabled, regardless of the
state of any of the other bits or pins.
2.9.5 EN_Fout bit -- Fout port enable
This bit enables the Fout pin.
2.9.6 PLL_R_DLY [3:0] - Global Skew Adjust, Lag
These bits control the delay stage in front of the R input of the
phase detector. The affect of adjusting this delay is to lag the
phase of the clock outputs uniformly from the clock input
phase by the specified amount.
2.10 REGISTER R15
Programming R15 also activates the frequency calibration
routine while 0_DELAY_MODE = 0. Programming R15 also
causes a global synchronization operation. See sections
2.4.3 0_DELAY_MODE bit -- Activate 0-Delay Mode
GLOBAL CLOCK OUTPUT SYNCHRONIZATION
tively for more information.
2.10.1 PLL_N [17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider.
The PLL N Divider follows the VCO Divider and precedes the
EN_CLKout_Global bit
POWERDOWN bit
PLL_R_DLY[3:0]
EN_Fout bit
0
1
0
1
0
1
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Entire Device Powered Down
Normal Operation (default)
Normal Operation (default)
Disabled (default)
Fout Pin Status
Clock Outputs
Enabled
Delay (ps)
All Off
Mode
0 (default)
1050
1200
1350
1500
1650
1800
1950
2100
2250
150
300
450
600
750
900
and
respec-
1.6