MPC8241LZQ200D Freescale Semiconductor, MPC8241LZQ200D Datasheet - Page 43

IC MPU 32BIT 200MHZ PPC 357-PBGA

MPC8241LZQ200D

Manufacturer Part Number
MPC8241LZQ200D
Description
IC MPU 32BIT 200MHZ PPC 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8241LZQ200D

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
200MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
MPC82XX
Device Core
PowerQUICC II
Device Core Size
32b
Frequency (max)
200MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

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Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with
minimal inductance of vias.
7.2
Dynamic power management, large address and data buses, and high operating frequencies enable the
MPC8241 to generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Therefore,
place at least one decoupling capacitor at each V
capacitors receive their power from dedicated power planes in the PCB, using short traces to minimize
inductance. These capacitors should have a value of 0.1 µF. To minimize lead inductance, use only ceramic
SMT (surface mount technology) capacitors, preferably 0508 or 0603, on which connections are made
along the length of the part.
In addition, distribute several bulk storage capacitors around the PCB to feed the V
LV
have a low ESR (equivalent series resistance) rating to ensure the necessary quick response time, and
should be connected to the power and ground planes through two vias to minimize inductance. Freescale
recommends using bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
7.3
To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low
inputs to OV
unconnected.
Power and ground connections must be made to all external V
The PCI_SYNC_OUT signal is to be routed halfway out to the PCI devices and then returned to the
PCI_SYNC_IN input.
The SDRAM_SYNC_OUT signal is to be routed halfway out to the SDRAM devices and then returned to
the SDRAM_SYNC_IN input of the MPC8241. The trace length can be used to skew or adjust the timing
window as needed. See the Tundra Tsi107™ Design Guide (AN1849) and Freescale application notes
AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines: Part 1 and AN2746,
MPC8245/MPC8241 Memory Clock Design Guidelines: Part 2 for more details. Note the
SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see
Freescale Semiconductor
DD
planes and enable quick recharging of the smaller chip capacitors. These bulk capacitors should
Decoupling Recommendations
Connection Recommendations
DD
. Connect unused active-high inputs to GND. All no connect (NC) signals must remain
V
DD
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Figure 26. PLL Power Supply Filter Circuit
10 Ω
2.2 µF
DD
GND
, GV
Low ESL Surface Mount Capacitors
DD
2.2 µF
_OV
DD
Table
DD
, GV
, and LV
10).
AV
DD
DD
_OV
or AV
DD
DD
DD
pin. These decoupling
, LV
2
DD
System Design Information
, GV
DD
, and GND pins.
DD
_OV
DD
, and
43

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