MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 14

• Manufacturer Part Number: MPC8349ECVVAGDB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8349ECVVAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

RESET Initialization
5.2
Table 10
14
Required assertion time of HRESET or SRESET (input) to activate reset flow
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8349EA is in PCI host mode
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8349EA is in PCI agent mode
HRESET/SRESET assertion (output)
HRESET negation to SRESET negation (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI host mode
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI agent mode
Input hold time for POR configuration signals with respect to negation of HRESET
Time for the MPC8349EA to turn off POR configuration signals with respect to the
assertion of HRESET
Time for the MPC8349EA to turn on POR configuration signals with respect to the
negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Output low voltage
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus V
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
PCI_SYNC_IN
CLKIN
is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
provides the reset initialization AC timing specifications of the MPC8349EA.
RESET AC Electrical Characteristics
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
Parameter
Table 9. RESET Pins DC Electrical Characteristics
Table 10. RESET Initialization Timing Specifications
Parameter
OH
Symbol
is not relevant for those pins.
V
OL
I
OL
Condition
= 3.2 mA
1
(continued)
Min
512
32
32
32
16
—
4
4
0
1
Min
—
Max
—
—
—
—
—
—
—
—
—
4
Freescale Semiconductor
Max
t
t
t
t
t
t
0.4
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
t
t
CLKIN
CLKIN
Unit
ns
ns
Unit
Notes
V
1, 3
—
1
2
1
1
1
2
1
3