MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 2

IC MPU POWERQUICC II 672-TBGA

MPC8349ECVVAGDB

Manufacturer Part Number
MPC8349ECVVAGDB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8349ECVVAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
672-TBGA
For Use With
MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8349ECVVAGDB
Manufacturer:
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Quantity:
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Part Number:
MPC8349ECVVAGDB
Manufacturer:
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Quantity:
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Overview
1
This section provides a high-level overview of the device features.
units within the MPC8349EA.
Major features of the device are as follows:
2
DDR/DD
SDRAM
USB0
GPIO
Serial
USB1
ROM
IRQs
Overview
I
Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
SPI
2
C
R2
Architecture technology
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See
silicon revision level determination.
Programmable Interrupt
Local Bus Controller
General Purpose I/O
Security Engine
Section 22.1, “Part Numbers Fully Addressed by This Document,”
Memory Controller
USB Hi-Speed
Serial Peripheral
I
2
Host Device
DDR/DDR2
C Interfaces
Controller
DUART
Interface
Figure 1. MPC8349EA Block Diagram
Sequencer
NOTE
Arbiter Bus
Monitor
SEQ
Coherent System Bus
64/32b PCI Controller
10/100/1Gb
10/100/1Gb
0/32b PCI Controller
Figure 1
TSEC
TSEC
DMA Controller
shows the major functional
32-Kbyte L1
Instruction
Cache
MII, GMII, TBI,
RTBI, RGMII
MII, GMII, TBI,
RTBI, RGMII
e300 Core
Freescale Semiconductor
for
32-Kbyte
L1 Data
PCI1
PCI2
DMA
Cache

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