MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 43

• Manufacturer Part Number: MPC8349ECVVAGDB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8349ECVVAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 26
Figure 27
Figure 28
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
and t
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
went invalid (X) relative to the t
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
External Clock
Table 41. JTAG AC Timing Specifications (Independent of CLKIN)
TRST
Parameter
JTAG
Output
JTG
Figure 26. AC Test Load for the JTAG Interface
Figure 27. JTAG Clock Input Timing Diagram
Boundary-scan data
clock reference (K) going to the high (H) state. In general, the clock reference symbol is
Table
VM
t
JTKHKL
JTDXKH
Figure 28. TRST Timing Diagram
2).
VM
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
TCLK
Z
t
JTG
TCLK
0
symbolizes JTAG timing (JT) with respect to the time data input signals (D)
= 50 Ω
TDO
.
VM
.
t
TRST
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
Symbol
t
t
JTKLOZ
JTKLDZ
VM
2
R
L
VM
= 50 Ω
Min
TCLK
t
2
2
JTGR
to the midpoint of the signal in question.
JTDVKH
OV
DD
1
Max
symbolizes JTAG device timing
19
t
9
(continued)
JTG
JTGF
/2
clock reference (K) going
Unit
ns
Figure
for inputs
17).
Notes
5, 6
JTAG
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