MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 85

IC MPU POWERQUICC II 672-TBGA

MPC8349ECVVAGDB

Manufacturer Part Number
MPC8349ECVVAGDB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8349ECVVAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
672-TBGA
For Use With
MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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MPC8349ECVVAGDB
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Freescale Semiconductor
Number
Rev.
9
8
7
6
5
4
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
12/2006
2/2009
4/2007
3/2007
2/2007
1/2007
Date
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T
from 900 ps to 775 ps.
• Added footnote 6 to
• In
• In
• Added footnote 11 to
• Added footnote 4 to
• In
• In
• In
• In
• In
• In
• In
• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
• In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’
• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
• In Section 23, “Ordering Information,” replaced first paragraph and added a note.
• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to t
• In Figure 41, “JTAG Interface Connection,” updated with new figure.
• In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced third sentence of
• In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency) to max
• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply
• In Table 4, “MPC8349EA Power Dissipation,” added two footnotes to 667-MHz row showing
• In Table 54, “MPC83479EA (TBGA) Pinout Listing,” updated V
in DLL bypass mode). Similarly, made the same correction to
for output signals.
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
is limited to 533 with a platform frequency of 266.”
added USB to the seventh row.
paragraph, added a new paragraph.
row, changed the value in the 533 MHz column to 100-333.
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,
changed the CORE PLL value to 0000110.
and deleted original note 3; renumbered the remaining notes.
first paragraph directing customer to product summary page for available frequency configuration
parts.
V
voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
DD
Table
Table
Section 9.2, “USB AC Electrical
Section 21.1, “System
Section 21.2, “PLL Power Supply
Table
Table
Table
Section 21.7, “Pull-Up Resistor
Table 68. Document Revision History (continued)
and Av
39, corrected t
66, updated note 1 to say the following: “For temperature range = C, processor frequency
57, corrected the max csb_clk to 266 MHz.
62, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz
3,
“Output Drive Capability,”
DD
values.
Table
Table
Table
LBKHOV
Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
7.
66.
55.
parameter to t
Requirements,“deleted last two paragraphs and after first
Substantive Change(s)
Specifications,” clarified that AC table is for ULPI only.
Filtering,” in the second paragraph, changed “provide five
changed the values in the Output Impedance column and
LBKLOV
(output data is driven on falling edge of clock
Figure
DD
nd AV
21,
Document Revision History
DD
Figure
rows to show nominal
ddkhds
23, and
for 333 MHz
Figure 24
CISKEW
85

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