MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 66

IC MPU POWERQUICC II 672-TBGA

MPC8349ECVVAGDB

Manufacturer Part Number
MPC8349ECVVAGDB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8349ECVVAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
672-TBGA
For Use With
MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Clocking
19 Clocking
Figure 40
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.
66
CFG_CLKIN_DIV
shows the internal distribution of the clocks.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
CLKIN
System PLL
Figure 40. MPC8349EA Clock Subsystem
e300 Core
PCI Clock
csb_clk
Clock
Divider
Unit
csb_clk to Rest
of the Device
ddr_clk
lbiu_clk
Core PLL
To Local Bus
Controller
Memory
Controller
To DDR
Memory
Clock
DDR
LBIU
/n
DLL
Div
/2
core_clk
6
6
8
MCK[0:5]
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
MCK[0:5]
PCI_SYNC_OUT
PCI_CLK_OUT[0:7]
PCI_CLK/
PCI_SYNC_IN
Freescale Semiconductor
DDR
Memory
Device
Local Bus
Memory
Device

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