MPC8349ECVVAGDB Freescale Semiconductor, MPC8349ECVVAGDB Datasheet - Page 27

• Manufacturer Part Number: MPC8349ECVVAGDB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8349ECVVAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.2.2.2
Table 28
Figure 11
Figure 12
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols for timing specifications follow the pattern of t
and t
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the MII receive AC timing specifications.
provides the AC test load for TSEC.
shows the MII receive AC timing diagram.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
MII Receive AC Timing Specifications
RXD[3:0]
Parameter/Condition
RX_CLK
RX_DV
RX_ER
Output
Table 28. MII Receive AC Timing Specifications
MRX
Figure 12. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
MRDXKL
clock reference (K) going to the low (L) state or hold time. In general, the clock
/OV
Figure 11. TSEC AC Test Load
t
DD
MRX
symbolizes MII receive timing (GR) with respect to the time data input signals
of 3.3 V ± 10%.
Z
0
= 50 Ω
Valid Data
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MRXH
Symbol
t
t
t
MRXF
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
MRX
1
R
t
MRDXKH
L
t
MRXR
= 50 Ω
Ethernet: Three-Speed Ethernet, MII Management
10.0
10.0
Min
1.0
1.0
35
—
—
MRDVKH
OV
MRX
DD
Typ
400
40
—
—
—
—
—
symbolizes MII receive timing
/2
clock reference (K) going to
Max
4.0
4.0
—
—
65
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%
MRX
27