MPC8270VVUPEA Freescale Semiconductor, MPC8270VVUPEA Datasheet - Page 23

• Manufacturer Part Number: MPC8270VVUPEA
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8270VVUPEA

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 450MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 450 MHz
• Operating Supply Voltage: 0 V to 3 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Program Memory Size: 16 KB
• Program Memory Type: EPROM/Flash
• Core Size: 32 Bit
• Cpu Speed: 450MHz
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7 Clock Configuration Modes
The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three
input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in
Freescale Semiconductor
Input hold times
Output valid times
Output hold times
JTAG external clock to output high impedance
1
2
3
4
5
6
7
All outputs are measured from the midpoint voltage of the falling/rising edge of t
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
The symbols used for timing specifications herein follow the pattern of t
for inputs and t(
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to t
Non-JTAG signal output timing with respect to t
Guaranteed by design.
Guaranteed by design and device characterization.
1
PCI_MODE
Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3.
1
0
0
0
0
(first two letters of functional block)(reference)(state)(signal)(state)
PCI_CFG[0] PCI_MODCK
Parameter
Pins
—
0
0
1
1
MPC8280 PowerQUICC™ II Family Hardware Specifications, Rev. 1.8
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
—
0
1
0
1
Table 14. JTAG Timings
Table 15. MPC8280 Clocking Modes
JTG
1
clock reference (K) going to the high (H) state. Note that, in general, the clock
TCLK
TMS, TDI
TCLK
.
JTDXKH
TDO
TDO
TDO
.
Clocking Mode
PCI agent
Local bus
PCI host
symbolizes JTAG timing (JT) with respect to the time data input
Symbol
t
t
t
t
t
t
t
t
JTDXKH
JTKLOV
JTKLOX
JTKLDV
JTKLDX
JTKLDZ
JTKLOZ
JTIXKH
1
2
(continued)
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
Table
Frequency Range
Min
10
10
—
—
TCLK
1
1
1
1
PCI Clock
15.
(MHZ)
50–66
25–50
50–66
25–50
to the midpoint of the signal in question.
—
Max
10
10
10
10
—
—
—
—
Clock Configuration Modes
JTDVKH
Unit
Reference
ns
ns
ns
ns
ns
ns
ns
ns
symbolizes JTAG
JTG
Table 16
Table 17
Table 18
Table 19
Table 20
clock reference
Notes
4
4
5
5
5
5
5
5
,
,
,
.
,
,
,
,
7
7
7
7
7
7
6
6
23